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Merge branch 'developer' of github.com:slsdetectorgroup/slsDetectorPackage into developer

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This commit is contained in:
Erik Frojdh 2019-10-07 14:18:06 +02:00
commit e0d10d0e01
14 changed files with 694 additions and 161 deletions
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1
slsDetectorServers/mythen3DetectorServer/CMakeLists.txt
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@ -7,6 +7,7 @@ add_executable(mythen3DetectorServer_virtual
../slsDetectorServer/src/communication_funcs_UDP.c
../slsDetectorServer/src/DAC6571.c
../slsDetectorServer/src/common.c
../slsDetectorServer/src/LTC2620_Driver.c
)
include_directories(

4
slsDetectorServers/mythen3DetectorServer/Makefile
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@ -5,14 +5,14 @@ support_lib = ../../slsSupportLib/include/
CROSS = nios2-buildroot-linux-gnu-
CC = $(CROSS)gcc
CFLAGS += -Wall -DMYTHEN3D -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir)#-DVERBOSEI #-DVERBOSE
CFLAGS += -Wall -DMYTHEN3D -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir) -DDEBUG1 #-DVERBOSEI #-DVERBOSE
LDLIBS += -lm
PROGS = mythen3DetectorServer
DESTDIR ?= bin
INSTMODE = 0777
SRCS = slsDetectorFunctionList.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)nios.c $(main_src)DAC6571.c $(main_src)common.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)nios.c $(main_src)DAC6571.c $(main_src)common.c $(main_src)LTC2620_Driver.c
OBJS = $(SRCS:.c=.o)

142
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -2,14 +2,19 @@
#pragma once
/* Definitions for FPGA*/
#define REG_OFFSET (4)
#define BASE_CONTROL (0x0)
#define BASE_PATTERN_CONTROL (0x200)
#define BASE_PATTERN_RAM (0x10000)
#define BASE_UDP_RAM (0x1000) // fix it
/* Basic detector FPGA registers --------------------------------------------------*/
/* Module Control Board Serial Number Register */
#define MCB_SERIAL_NO_REG (0x000 * REG_OFFSET + BASE_CONTROL)
/* FPGA Version register */
#define FPGA_VERSION_REG (0x04 + BASE_CONTROL)
#define FPGA_VERSION_REG (0x001 * REG_OFFSET + BASE_CONTROL)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
@ -17,64 +22,67 @@
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* Module Control Board Serial Number Register */
#define MCB_SERIAL_NO_REG (0x00 + BASE_CONTROL)
/* API Version Register */
#define API_VERSION_REG (0x08 + BASE_CONTROL)
#define API_VERSION_REG (0x002 * REG_OFFSET + BASE_CONTROL)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
/* Fix pattern register */
#define FIX_PATT_REG (0x0C + BASE_CONTROL)
#define FIX_PATT_REG (0x003 * REG_OFFSET + BASE_CONTROL)
#define FIX_PATT_VAL (0xACDC2019)
/* Status register */
#define STATUS_REG (0x10 + BASE_CONTROL)
#define STATUS_REG (0x004 * REG_OFFSET + BASE_CONTROL)
#ifdef VIRTUAL // until firmware is ready ----------------------------------
#define RUN_BUSY_OFST (0)
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
#endif
/* Look at me register */
#define LOOK_AT_ME_REG (0x14 + BASE_CONTROL) //Not used in firmware or software, good to play with
/* Look at me register, read only */
#define LOOK_AT_ME_REG (0x005 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with
#define DTA_OFFSET_REG (0x104 * REG_OFFSET + BASE_CONTROL)
/* Pattern Control FPGA registers --------------------------------------------------*/
/* Pattern status Register*/
#define PAT_STATUS_REG (0x00 + BASE_PATTERN_CONTROL)
#define PAT_STATUS_REG (0x000 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Delay left 64bit Register */
#define GET_DELAY_LSB_REG (0x08 + BASE_PATTERN_CONTROL)
#define GET_DELAY_MSB_REG (0x0C + BASE_PATTERN_CONTROL)
#define GET_DELAY_LSB_REG (0x0002 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_DELAY_MSB_REG (0x0003 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Cycles left 64bit Register */
#define GET_CYCLES_LSB_REG (0x10 + BASE_PATTERN_CONTROL)
#define GET_CYCLES_MSB_REG (0x14 + BASE_PATTERN_CONTROL)
#define GET_CYCLES_LSB_REG (0x0004 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_CYCLES_MSB_REG (0x0005 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Frames left 64bit Register */
#define GET_FRAMES_LSB_REG (0x18 + BASE_PATTERN_CONTROL)
#define GET_FRAMES_MSB_REG (0x1C + BASE_PATTERN_CONTROL)
#define GET_FRAMES_LSB_REG (0x0006 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_FRAMES_MSB_REG (0x0007 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Period left 64bit Register */
#define GET_PERIOD_LSB_REG (0x20 + BASE_PATTERN_CONTROL)
#define GET_PERIOD_MSB_REG (0x24 + BASE_PATTERN_CONTROL)
#define GET_PERIOD_LSB_REG (0x0008 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_PERIOD_MSB_REG (0x0009 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Delay 64bit Write-register */
#define SET_DELAY_LSB_REG (0x88 + BASE_PATTERN_CONTROL)
#define SET_DELAY_MSB_REG (0x8C + BASE_PATTERN_CONTROL)
#define SET_DELAY_LSB_REG (0x0102 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_DELAY_MSB_REG (0x0103 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Cylces 64bit Write-register */
#define SET_CYCLES_LSB_REG (0x90 + BASE_PATTERN_CONTROL)
#define SET_CYCLES_MSB_REG (0x94 + BASE_PATTERN_CONTROL)
#define SET_CYCLES_LSB_REG (0x0104 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_CYCLES_MSB_REG (0x0105 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Frames 64bit Write-register */
#define SET_FRAMES_LSB_REG (0x98 + BASE_PATTERN_CONTROL)
#define SET_FRAMES_MSB_REG (0x9C + BASE_PATTERN_CONTROL)
#define SET_FRAMES_LSB_REG (0x0106 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_FRAMES_MSB_REG (0x0107 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Period 64bit Write-register */
#define SET_PERIOD_LSB_REG (0xA0 + BASE_PATTERN_CONTROL)
#define SET_PERIOD_MSB_REG (0xA4 + BASE_PATTERN_CONTROL)
#define SET_PERIOD_LSB_REG (0x0108 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_PERIOD_MSB_REG (0x0109 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Control FPGA registers --------------------------------------------------*/
@ -85,76 +93,78 @@
// #define PATTERN_IO_CNTRL_MSB_REG (0x8C + BASE_CONTROL)
/* Pattern Limit RW Register */
#define PATTERN_LIMIT_REG (0x100 + BASE_PATTERN_CONTROL)
#define PATTERN_LIMIT_REG (0x1000 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/* Pattern Wait Timer 0 64bit RW Register */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x1100 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x1101 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 0 RW Register*/
#define PATTERN_WAIT_0_ADDR_REG (0x188 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_0_ADDR_REG (0x1102 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
/* Pattern Wait 1 RW Register*/
#define PATTERN_WAIT_1_ADDR_REG (0x19C + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW Register*/
#define PATTERN_WAIT_2_ADDR_REG (0x1B0 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Pattern Wait Timer 0 64bit RW Register */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x180 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x184 + BASE_PATTERN_CONTROL)
/* Pattern Wait Timer 1 64bit RW Register */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x194 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x198 + BASE_PATTERN_CONTROL)
/* Pattern Wait Timer 2 64bit RW Register */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x1A8 + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x1AC + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Iteration RW Register */
#define PATTERN_LOOP_0_ITERATION_REG (0x1103 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_0_ADDR_REG (0x190 + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_REG (0x1104 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Wait Timer 1 64bit RW Register */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x1105 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x1106 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 1 RW Register*/
#define PATTERN_WAIT_1_ADDR_REG (0x1107 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Loop 1 Iteration RW Register */
#define PATTERN_LOOP_1_ITERATION_REG (0x1108 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
/* Pattern Loop 1 Address RW Register */
#define PATTERN_LOOP_1_ADDR_REG (0x1A4 + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_REG (0x1109 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Wait Timer 2 64bit RW Register */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x110A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x110B * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 2 RW Register*/
#define PATTERN_WAIT_2_ADDR_REG (0x110C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Pattern Loop 2 Iteration RW Register */
#define PATTERN_LOOP_2_ITERATION_REG (0x110D * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_2_ADDR_REG (0x1B8 + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_REG (0x110E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW Register */
#define PATTERN_LOOP_0_ITERATION_REG (0x18C + BASE_PATTERN_CONTROL) // patnloop
/* Pattern Loop 1 Iteration RW Register */
#define PATTERN_LOOP_1_ITERATION_REG (0x1A0 + BASE_PATTERN_CONTROL) // patnloop
/* Pattern Loop 2 Iteration RW Register */
#define PATTERN_LOOP_2_ITERATION_REG (0x1B4 + BASE_PATTERN_CONTROL) // patnloop
/* Register of first word */
#define PATTERN_STEP0_LSB_REG (0x0 + BASE_PATTERN_RAM)
#define PATTERN_STEP0_MSB_REG (0x4 + BASE_PATTERN_RAM)
#define PATTERN_STEP0_LSB_REG (0x0 * REG_OFFSET + BASE_PATTERN_RAM)
#define PATTERN_STEP0_MSB_REG (0x1 * REG_OFFSET + BASE_PATTERN_RAM)

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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Binary file not shown.

298
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -3,6 +3,7 @@
#include "clogger.h"
#include "nios.h"
#include "DAC6571.h"
#include "LTC2620_Driver.h"
#include "common.h"
#include "RegisterDefs.h"
@ -36,6 +37,7 @@ int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0};
uint32_t clkDivider[NUM_CLOCKS] = {125, 20, 80};
int highvoltage = 0;
int dacValues[NDAC] = {0};
int detPos[2] = {0, 0};
int isFirmwareCheckDone() {
@ -74,7 +76,7 @@ void basictests() {
return;
}
// does check only if flag is 0 (by default), set by command line
if ((!debugflag) && ((testFpga() == FAIL))) {
if ((!debugflag) && ((testFpga() == FAIL)|| (testBus() == FAIL))) {
strcpy(firmware_message,
"Could not pass basic tests of FPGA and bus. Dangerous to continue.\n");
FILE_LOG(logERROR, ("%s\n\n", firmware_message));
@ -82,10 +84,89 @@ void basictests() {
firmware_check_done = 1;
return;
}
uint16_t hversion = getHardwareVersionNumber();
uint32_t ipadd = getDetectorIP();
uint64_t macadd = getDetectorMAC();
int64_t fwversion = getDetectorId(DETECTOR_FIRMWARE_VERSION);
int64_t swversion = getDetectorId(DETECTOR_SOFTWARE_VERSION);
int64_t sw_fw_apiversion = 0;
int64_t client_sw_apiversion = getDetectorId(CLIENT_SOFTWARE_API_VERSION);
uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
sw_fw_apiversion = getDetectorId(SOFTWARE_FIRMWARE_API_VERSION);
FILE_LOG(logINFOBLUE, ("************ Mythen3 Server *********************\n"
"Hardware Version:\t\t 0x%x\n"
"Detector IP Addr:\t\t 0x%x\n"
"Detector MAC Addr:\t\t 0x%llx\n\n"
"Firmware Version:\t\t 0x%llx\n"
"Software Version:\t\t 0x%llx\n"
"F/w-S/w API Version:\t\t 0x%llx\n"
"Required Firmware Version:\t 0x%x\n"
"Client-Software API Version:\t 0x%llx\n"
"********************************************************\n",
hversion,
ipadd,
(long long unsigned int)macadd,
(long long int)fwversion,
(long long int)swversion,
(long long int)sw_fw_apiversion,
requiredFirmwareVersion,
(long long int)client_sw_apiversion
));
// return if flag is not zero, debug mode
if (debugflag) {
firmware_check_done = 1;
return;
}
//cant read versions
FILE_LOG(logINFO, ("Testing Firmware-software compatibility:\n"));
if(!fwversion || !sw_fw_apiversion){
strcpy(firmware_message,
"Cant read versions from FPGA. Please update firmware.\n");
FILE_LOG(logERROR, (firmware_message));
firmware_compatibility = FAIL;
firmware_check_done = 1;
return;
}
//check for API compatibility - old server
if(sw_fw_apiversion > requiredFirmwareVersion){
sprintf(firmware_message,
"This detector software software version (0x%llx) is incompatible.\n"
"Please update detector software (min. 0x%llx) to be compatible with this firmware.\n",
(long long int)sw_fw_apiversion,
(long long int)requiredFirmwareVersion);
FILE_LOG(logERROR, (firmware_message));
firmware_compatibility = FAIL;
firmware_check_done = 1;
return;
}
//check for firmware compatibility - old firmware
if( requiredFirmwareVersion > fwversion) {
sprintf(firmware_message,
"This firmware version (0x%llx) is incompatible.\n"
"Please update firmware (min. 0x%llx) to be compatible with this server.\n",
(long long int)fwversion,
(long long int)requiredFirmwareVersion);
FILE_LOG(logERROR, (firmware_message));
firmware_compatibility = FAIL;
firmware_check_done = 1;
return;
}
FILE_LOG(logINFO, ("Compatibility - success\n"));
firmware_check_done = 1;
#endif
}
int checkType() {
#ifdef VIRTUAL
return OK;
@ -117,6 +198,34 @@ int testFpga() {
return ret;
}
int testBus() {
#ifdef VIRTUAL
return OK;
#endif
FILE_LOG(logINFO, ("Testing Bus:\n"));
int ret = OK;
u_int32_t addr = DTA_OFFSET_REG;
int times = 1000 * 1000;
int i = 0;
for (i = 0; i < times; ++i) {
bus_w(addr, i * 100);
if (i * 100 != bus_r(addr)) {
FILE_LOG(logERROR, ("Mismatch! Wrote 0x%x, read 0x%x\n",
i * 100, bus_r(addr)));
ret = FAIL;
}
}
bus_w(addr, 0);
if (ret == OK) {
FILE_LOG(logINFO, ("Successfully tested bus %d times\n", times));
}
return ret;
}
/* Ids */
int64_t getDetectorId(enum idMode arg){
@ -141,21 +250,28 @@ u_int64_t getFirmwareVersion() {
#ifdef VIRTUAL
return 0;
#endif
return 0;
return ((bus_r(FPGA_VERSION_REG) & FPGA_COMPILATION_DATE_MSK) >> FPGA_COMPILATION_DATE_OFST);
}
u_int64_t getFirmwareAPIVersion() {
#ifdef VIRTUAL
return 0;
#endif
return ((bus_r(API_VERSION_REG) & API_VERSION_MSK) >> API_VERSION_OFST);
}
u_int16_t getHardwareVersionNumber() {
#ifdef VIRTUAL
return 0;
#endif
return bus_r(MCB_SERIAL_NO_REG);
}
u_int32_t getDetectorNumber(){
#ifdef VIRTUAL
return 0;
#endif
return 0;
return bus_r(MCB_SERIAL_NO_REG);
}
@ -236,8 +352,11 @@ void setupDetector() {
#ifndef VIRTUAL
// hv
DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
//dac
LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
#endif
setHighVoltage(DEFAULT_HIGH_VOLTAGE);
setDefaultDacs();
// Initialization of acquistion parameters
setTimer(FRAME_NUMBER, DEFAULT_NUM_FRAMES);
@ -246,9 +365,23 @@ void setupDetector() {
setTimer(ACQUISITION_TIME, DEFAULT_EXPTIME);
setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY_AFTER_TRIGGER);
}
int setDefaultDacs() {
int ret = OK;
FILE_LOG(logINFOBLUE, ("Setting Default Dac values\n"));
{
int i = 0;
const int defaultvals[NDAC] = DEFAULT_DAC_VALS;
for(i = 0; i < NDAC; ++i) {
// if not already default, set it to default
if (dacValues[i] != defaultvals[i]) {
setDAC((enum DACINDEX)i,defaultvals[i],0);
}
}
}
return ret;
}
/* set parameters - dr, roi */
@ -352,6 +485,7 @@ int validateTimer(enum timerIndex ind, int64_t val, int64_t retval) {
break;
}
return OK;
}
@ -379,6 +513,44 @@ int64_t getTimeLeft(enum timerIndex ind){
return retval;
}
/* parameters - dac, hv */
void setDAC(enum DACINDEX ind, int val, int mV) {
if (val < 0)
return;
FILE_LOG(logDEBUG1, ("Setting dac[%d]: %d %s \n", (int)ind, val, (mV ? "mV" : "dac units")));
int dacval = val;
#ifdef VIRTUAL
if (!mV) {
dacValues[ind] = val;
}
// convert to dac units
else if (LTC2620_D_VoltageToDac(val, &dacval) == OK) {
dacValues[ind] = dacval;
}
#else
if (LTC2620_D_SetDACValue((int)ind, val, mV, &dacval) == OK) {
dacValues[ind] = dacval;
}
#endif
}
int getDAC(enum DACINDEX ind, int mV) {
if (!mV) {
FILE_LOG(logDEBUG1, ("Getting DAC %d : %d dac\n",ind, dacValues[ind]));
return dacValues[ind];
}
int voltage = -1;
LTC2620_D_DacToVoltage(dacValues[ind], &voltage);
FILE_LOG(logDEBUG1, ("Getting DAC %d : %d dac (%d mV)\n",ind, dacValues[ind], voltage));
return voltage;
}
int getMaxDacSteps() {
return LTC2620_D_GetMaxNumSteps();
}
int setHighVoltage(int val){
// limit values
if (val > HV_SOFT_MAX_VOLTAGE ) {
@ -401,10 +573,15 @@ int setHighVoltage(int val){
int configureMAC() {
#ifdef VIRTUAL
uint32_t srcip = udpDetails.srcip;
uint32_t dstip = udpDetails.dstip;
uint64_t srcmac = udpDetails.srcmac;
uint64_t dstmac = udpDetails.dstmac;
int srcport = udpDetails.srcport;
int dstport = udpDetails.dstport;
#ifdef VIRTUAL
char cDestIp[MAX_STR_LENGTH];
memset(cDestIp, 0, MAX_STR_LENGTH);
sprintf(cDestIp, "%d.%d.%d.%d", (dstip>>24)&0xff,(dstip>>16)&0xff,(dstip>>8)&0xff,(dstip)&0xff);
@ -414,9 +591,108 @@ int configureMAC() {
return FAIL;
}
#endif
FILE_LOG(logINFOBLUE, ("Configuring MAC\n"));
FILE_LOG(logINFO, ("\tSource IP : %d.%d.%d.%d \t\t(0x%08x)\n",
(srcip>>24)&0xff,(srcip>>16)&0xff,(srcip>>8)&0xff,(srcip)&0xff, srcip));
FILE_LOG(logINFO, ("\tSource MAC : %02x:%02x:%02x:%02x:%02x:%02x \t(0x%010llx)\n",
(unsigned int)((srcmac>>40)&0xFF),
(unsigned int)((srcmac>>32)&0xFF),
(unsigned int)((srcmac>>24)&0xFF),
(unsigned int)((srcmac>>16)&0xFF),
(unsigned int)((srcmac>>8)&0xFF),
(unsigned int)((srcmac>>0)&0xFF),
(long long unsigned int)srcmac));
FILE_LOG(logINFO, ("\tSource Port : %d \t\t\t(0x%08x)\n", srcport, srcport));
FILE_LOG(logINFO, ("\tDest. IP : %d.%d.%d.%d \t\t(0x%08x)\n",
(dstip>>24)&0xff,(dstip>>16)&0xff,(dstip>>8)&0xff,(dstip)&0xff, dstip));
FILE_LOG(logINFO, ("\tDest. MAC : %02x:%02x:%02x:%02x:%02x:%02x \t(0x%010llx)\n",
(unsigned int)((dstmac>>40)&0xFF),
(unsigned int)((dstmac>>32)&0xFF),
(unsigned int)((dstmac>>24)&0xFF),
(unsigned int)((dstmac>>16)&0xFF),
(unsigned int)((dstmac>>8)&0xFF),
(unsigned int)((dstmac>>0)&0xFF),
(long long unsigned int)dstmac));
FILE_LOG(logINFO, ("\tDest. Port : %d \t\t\t(0x%08x)\n\n",dstport, dstport));
// start addr
uint32_t addr = BASE_UDP_RAM;
// calculate rxr endpoint offset
//addr += (iRxEntry * RXR_ENDPOINT_OFST);//TODO: is there round robin already implemented?
// get struct memory
udp_header *udp = (udp_header*) (Nios_getBaseAddress() + addr/(sizeof(u_int32_t)));
memset(udp, 0, sizeof(udp_header));
// mac addresses
// msb (32) + lsb (16)
udp->udp_destmac_msb = ((dstmac >> 16) & BIT32_MASK);
udp->udp_destmac_lsb = ((dstmac >> 0) & BIT16_MASK);
// msb (16) + lsb (32)
udp->udp_srcmac_msb = ((srcmac >> 32) & BIT16_MASK);
udp->udp_srcmac_lsb = ((srcmac >> 0) & BIT32_MASK);
// ip addresses
udp->ip_srcip_msb = ((srcip >> 16) & BIT16_MASK);
udp->ip_srcip_lsb = ((srcip >> 0) & BIT16_MASK);
udp->ip_destip_msb = ((dstip >> 16) & BIT16_MASK);
udp->ip_destip_lsb = ((dstip >> 0) & BIT16_MASK);
// source port
udp->udp_srcport = srcport;
udp->udp_destport = dstport;
// other defines
udp->udp_ethertype = 0x800;
udp->ip_ver = 0x4;
udp->ip_ihl = 0x5;
udp->ip_flags = 0x2; //FIXME
udp->ip_ttl = 0x40;
udp->ip_protocol = 0x11;
// total length is redefined in firmware
// calcChecksum(udp);
//TODO?
//cleanFifos();
//resetCore();
//alignDeserializer();
return OK;
}
void calcChecksum(udp_header* udp) {
int count = IP_HEADER_SIZE;
long int sum = 0;
// start at ip_tos as the memory is not continous for ip header
uint16_t *addr = (uint16_t*) (&(udp->ip_tos));
sum += *addr++;
count -= 2;
// ignore ethertype (from udp header)
addr++;
// from identification to srcip_lsb
while( count > 2 ) {
sum += *addr++;
count -= 2;
}
// ignore src udp port (from udp header)
addr++;
if (count > 0)
sum += *addr; // Add left-over byte, if any
while (sum >> 16)
sum = (sum & 0xffff) + (sum >> 16);// Fold 32-bit sum to 16 bits
long int checksum = sum & 0xffff;
checksum += UDP_IP_HEADER_LENGTH_BYTES;
FILE_LOG(logINFO, ("\tIP checksum is 0x%lx\n",checksum));
udp->ip_checksum = checksum;
}
/* pattern */
uint64_t readPatternWord(int addr) {
@ -427,9 +703,9 @@ uint64_t readPatternWord(int addr) {
return -1;
}
FILE_LOG(logINFORED, (" Reading (Executing) Pattern Word (addr:0x%x)\n", addr));
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr; // the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr;
FILE_LOG(logINFORED, (" Reading Pattern Word (addr:0x%x)\n", addr));
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2; // the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr * REG_OFFSET * 2;
// read value
uint64_t retval = get64BitReg(reg_lsb, reg_msb);
@ -451,8 +727,8 @@ uint64_t writePatternWord(int addr, uint64_t word) {
}
FILE_LOG(logINFO, ("Setting Pattern Word (addr:0x%x, word:0x%llx)\n", addr, (long long int) word));
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr; // the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr;
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2; // the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr * REG_OFFSET * 2;
// write word
set64BitReg(word, reg_lsb, reg_msb);
@ -503,7 +779,7 @@ int setPatternWaitAddress(int level, int addr) {
}
// get
uint32_t regval = bus_r((reg & mask) >> offset);
uint32_t regval = ((bus_r(reg) & mask) >> offset);
FILE_LOG(logDEBUG1, (" Wait Address retval (level:%d, addr:0x%x)\n", level, regval));
return regval;
}

73
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
View File

@ -1,6 +1,8 @@
#pragma once
#include "sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN 0x190000
#define MIN_REQRD_VRSN_T_RD_API 0x190000
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -11,6 +13,8 @@
#define HV_SOFT_MAX_VOLTAGE (200)
#define HV_HARD_MAX_VOLTAGE (530)
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
#define DAC_MAX_MV (2048)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
@ -23,29 +27,58 @@
#define DEFAULT_TICK_CLK (20) // will be fixed later. Not configurable
#define DEFAULT_SAMPLING_CLK (80)
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
/* Enums */
enum CLKINDEX {RUN_CLK, TICK_CLK, SAMPLING_CLK, NUM_CLOCKS};
enum DACINDEX {VIBIASSH, VTRIM, VIPRE, VRFSHNPOL, VTH1, VIPREOUT, VRF, VTH2, CAS, CASSH, VPL, VDCSH, VICIN, VICINSH, VICBIAS, VPH, VTH3, VRFSH};
#define DEFAULT_DAC_VALS {1200, /* vIbiasSh */ \
2300, /* vTrim */ \
2150, /* vIpre */ \
2300, /* VrfShNpol */ \
900, /* Vth1 */ \
1000, /* vIpreOut */ \
900, /* Vrf */ \
900, /* Vth2 */ \
1474, /* cas */ \
983, /* casSh */ \
900, /* VPL */ \
655, /* VdcSh */ \
1400, /* vIcin */ \
1400, /* vIcinSh */ \
1200, /* vIcbias */ \
960, /* VPH */ \
900, /* Vth3 */ \
1100 /* VrfSh */ \
enum DACINDEX {CASSH, VTH2, VRFSH, VRFSHNPOL, VIPREOUT, VTH3, VTH1, VICIN, CAS, VRF, VPH, VIPRE, VIINSH, VPL, VTRIM, VDCSH};
#define DEFAULT_DAC_VALS {1200, /* casSh */ \
2800, /* Vth2 */ \
1280, /* VrfSh */ \
2800, /* VrfShNpol */ \
1220, /* vIpreOut */ \
2800, /* Vth3 */ \
2800, /* Vth1 */ \
1708, /* vIcin */ \
1800, /* cas */ \
1100, /* Vrf */ \
1712, /* VPH */ \
2624, /* vIpre */ \
1708, /* vIinSh */ \
1100, /* VPL */ \
2800, /* vTrim */ \
800 /* VdcSh */ \
};
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x8192) // maximum number of words (64bit)
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
/* Struct Definitions */
typedef struct udp_header_struct {
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
} udp_header;
#define UDP_IP_HEADER_LENGTH_BYTES (28)

1
slsDetectorServers/slsDetectorServer/include/DAC6571.h
View File

@ -4,7 +4,6 @@
/**
* Set Defines
* @param dofst digital output offset
* @param hardMaxV maximum hardware limit
* @param driverfname driver file name
*/

43
slsDetectorServers/slsDetectorServer/include/LTC2620_Driver.h Executable file
View File

@ -0,0 +1,43 @@
#pragma once
#include <inttypes.h>
/**
* Set Defines
* @param hardMaxV maximum hardware limit
* @param driverfname driver file name
* @param numdacs number of dacs
*/
void LTC2620_D_SetDefines(int hardMaxV, char* driverfname, int numdacs);
/**
* Get max number of steps
*/
int LTC2620_D_GetMaxNumSteps();
/**
* Convert voltage to dac units
* @param voltage value in mv
* @param dacval pointer to value converted to dac units
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_D_VoltageToDac(int voltage, int* dacval);
/**
* Convert dac units to voltage
* @param dacval dac units
* @param voltage pointer to value converted to mV
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_D_DacToVoltage(int dacval, int* voltage);
/**
* Set value
* @param dacnum dac index
* @param val value to set
* @param mV 1 for mv, else 0
* @param dacval pointer to dac value
* @return OK or FAIL
*/
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, int *dacval);

8
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
View File

@ -51,8 +51,10 @@ int detectorTest(enum digitalTestMode arg);
int64_t getDetectorId(enum idMode arg);
u_int64_t getFirmwareVersion();
u_int64_t getFirmwareAPIVersion();
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
u_int16_t getHardwareVersionNumber();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
u_int16_t getHardwareSerialNumber();
#endif
#ifdef JUNGFRAUD
@ -83,7 +85,7 @@ int allocateRAM();
void updateDataBytes();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D)
int setDefaultDacs();
#endif
@ -210,7 +212,7 @@ extern int AD9257_GetVrefVoltage(int mV); // AD9257.h
extern int AD9257_SetVrefVoltage(int val, int mV); // AD9257.h
#endif
#if (!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
#if (!defined(GOTTHARD2D))
void setDAC(enum DACINDEX ind, int val, int mV);
int getDAC(enum DACINDEX ind, int mV);
int getMaxDacSteps();

90
slsDetectorServers/slsDetectorServer/src/LTC2620_Driver.c Executable file
View File

@ -0,0 +1,90 @@
#include "LTC2620_Driver.h"
#include "clogger.h"
#include "common.h"
#include "sls_detector_defs.h"
#include <string.h>
/* LTC2620 DAC DEFINES */
#define LTC2620_D_PWR_DOWN_VAL (-100)
#define LTC2620_D_MAX_DAC_VAL (4095) // 12 bits
#define LTC2620_D_MAX_STEPS (LTC2620_D_MAX_DAC_VAL + 1)
// defines from the fpga
int LTC2620_D_HardMaxVoltage = 0;
char LTC2620_D_DriverFileName[MAX_STR_LENGTH];
int LTC2620_D_NumDacs = 0;
void LTC2620_D_SetDefines(int hardMaxV, char* driverfname, int numdacs) {
FILE_LOG(logINFOBLUE, ("Configuring DACs (LTC2620)\n"));
LTC2620_D_HardMaxVoltage = hardMaxV;
memset(LTC2620_D_DriverFileName, 0, MAX_STR_LENGTH);
strcpy(LTC2620_D_DriverFileName, driverfname);
LTC2620_D_NumDacs = numdacs;
}
int LTC2620_D_GetMaxNumSteps() {
return LTC2620_D_MAX_STEPS;
}
int LTC2620_D_VoltageToDac(int voltage, int* dacval) {
return ConvertToDifferentRange(0, LTC2620_D_HardMaxVoltage, 0, LTC2620_D_MAX_DAC_VAL,
voltage, dacval);
}
int LTC2620_D_DacToVoltage(int dacval, int* voltage) {
return ConvertToDifferentRange( 0, LTC2620_D_MAX_DAC_VAL, 0, LTC2620_D_HardMaxVoltage,
dacval, voltage);
}
int LTC2620_D_SetDACValue (int dacnum, int val, int mV, int* dacval) {
FILE_LOG(logDEBUG1, ("dacnum:%d, val:%d, ismV:%d\n", dacnum, val, mV));
// validate index
if (dacnum < 0 || dacnum >= LTC2620_D_NumDacs) {
FILE_LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum, LTC2620_D_NumDacs - 1));
return FAIL;
}
// get
if (val < 0 && val != LTC2620_D_PWR_DOWN_VAL)
return FAIL;
// convert to dac or get mV value
*dacval = val;
int dacmV = val;
int ret = OK;
if (mV) {
ret = LTC2620_D_VoltageToDac(val, dacval);
} else if (val >= 0) {
// do not convert power down dac val
ret = LTC2620_D_DacToVoltage(val, &dacmV);
}
// conversion out of bounds
if (ret == FAIL) {
FILE_LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum, (mV ? "mV" : "dac units")));
return FAIL;
}
// set
if ( (*dacval >= 0) || (*dacval == LTC2620_D_PWR_DOWN_VAL)) {
FILE_LOG(logINFO, ("Setting DAC %d: %d dac (%d mV)\n",dacnum, *dacval, dacmV));
char fname[MAX_STR_LENGTH];
sprintf(fname, "%s%d", LTC2620_D_DriverFileName, dacnum);
FILE_LOG(logDEBUG1, ("fname %s\n",fname));
//open file
FILE* fd=fopen(fname,"w");
if (fd==NULL) {
FILE_LOG(logERROR, ("Could not open file %s for writing to set dac %d\n", fname, dacnum));
return FAIL;
}
//convert to string, add 0 and write to file
fprintf(fd, "%d\n", *dacval);
fclose(fd);
}
return OK;
}

53
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
View File

@ -847,6 +847,55 @@ int set_dac(int file_des) {
#elif MYTHEN3D
case HIGH_VOLTAGE:
break;
case M_casSh: // in sls_detector_defs.h
serverDacIndex = CASSH; // in mythen3 slsDetectorServer_defs.h
break;
case M_Vth2:
serverDacIndex = VTH2;
break;
case SHAPER1:
serverDacIndex = VRFSH;
break;
case SHAPER2:
serverDacIndex = VRFSHNPOL;
break;
case M_vIpreOut:
serverDacIndex = VIPREOUT;
break;
case M_Vth3:
serverDacIndex = VTH3;
break;
case THRESHOLD:
serverDacIndex = VTH1;
break;
case M_vIcin:
serverDacIndex = VICIN;
break;
case M_cas:
serverDacIndex = CAS;
break;
case PREAMP:
serverDacIndex = VRF;
break;
case CALIBRATION_PULSE:
serverDacIndex = VPH;
break;
case M_vIpre:
serverDacIndex = VIPRE;
break;
case M_vIinSh:
serverDacIndex = VIINSH;
break;
case M_VPL:
serverDacIndex = VPL;
break;
case TRIMBIT_SIZE:
serverDacIndex = VTRIM;
break;
case M_VdcSh:
serverDacIndex = VDCSH;
break;
#endif
default:
@ -1017,9 +1066,7 @@ int set_dac(int file_des) {
#ifdef GOTTHARD2D
default:
break;
#elif MYTHEN3D
default:
break;
#else
// dacs
default:

122
slsDetectorSoftware/src/slsDetectorCommand.cpp
View File

@ -934,6 +934,13 @@ slsDetectorCommand::slsDetectorCommand(multiSlsDetector *det) {
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>vhaper [i] [mv]</b> Sets/gets the voltage to define the feedback resistance of the shaper. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vshaper";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>vshaper2 [i] [mv]</b> Sets/gets the voltage to define the feedback resistance of the second shaper. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
@ -941,6 +948,13 @@ slsDetectorCommand::slsDetectorCommand(multiSlsDetector *det) {
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>vhaperneg [i] [mv]</b> Sets/gets the voltage to define the feedback resistance of the negative-polarity shaper. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vshaperneg";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>vhighvoltage [i]</b> Sets/gets the high voltage to the sensor in V. \c Returns \c (int ["mV"]).
*/
@ -1214,71 +1228,94 @@ slsDetectorCommand::slsDetectorCommand(multiSlsDetector *det) {
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/* MYTHEN 3.01
all values are in DACu */
descrToFuncMap[i].m_pFuncName = "vIpre";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "VcdSh";
/*! \page settings
- <b>vipre</b> Sets/gets dac for the current in the preamplifier for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vipre";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>Vth1</b> Sets/gets first detector threshold voltage for Mythen 3.01. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
- <b>vdcsh</b> Sets/gets dac for the baseline of the shaper for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "Vth1";
descrToFuncMap[i].m_pFuncName = "vdcsh";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>Vth1</b> Sets/gets second detector threshold voltage for Mythen 3.01. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
- <b>vth1</b> Sets/gets first detector threshold voltage for Mythen 3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "Vth2";
descrToFuncMap[i].m_pFuncName = "vth1";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>Vth1</b> Sets/gets third detector threshold voltage for Mythen 3.01. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
- <b>vth2</b> Sets/gets second detector threshold voltage for Mythen 3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "Vth3";
descrToFuncMap[i].m_pFuncName = "vth2";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "VPL"; //baseline for analog pulsing
/*! \page settings
- <b>vth3</b> Sets/gets third detector threshold voltage for Mythen 3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vth3";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "Vtrim";
/*! \page settings
- <b>vpl</b> Sets/gets dac for the lower value of the analog pulse for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vpl";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "vIbias";
/*! \page settings
- <b>vph</b> Sets/gets dac for the higher value of the analog pulse for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vph";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "vIinSh";
/*! \page settings
- <b>vtrim</b> Sets/gets dac for the voltage defining the trim bit size for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vtrim";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>viinsh</b> Sets/gets dac for xxx for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "viinsh";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
/*! \page settings
- <b>cas</b> Sets/gets dac for xxx for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "cas";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "casSh";
/*! \page settings
- <b>cassh</b> Sets/gets dac for xxx for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "cassh";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "vIbiasSh";
/*! \page settings
- <b>vicin</b> Sets/gets dac for the bias of the comparator for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vicin";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "vIcin";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
descrToFuncMap[i].m_pFuncName = "vIpreOut";
/*! \page settings
- <b>vipreout</b> Sets/gets dac for xxx for Mythen3. Normally in DAC units unless \c mv is specified at the end of the command line. \c Returns \c (int ["mV"])
*/
descrToFuncMap[i].m_pFuncName = "vipreout";
descrToFuncMap[i].m_pFuncPtr = &slsDetectorCommand::cmdDAC;
++i;
@ -1906,7 +1943,7 @@ std::string slsDetectorCommand::executeLine(int narg, const char * const args[],
if (action == READOUT_ACTION)
return cmdAcquire(narg, args, action, detPos);
xxx
size_t s = std::string(args[0]).find(':');
std::string key = std::string(args[0]).substr(0, s); // truncate at :
@ -3264,9 +3301,9 @@ std::string slsDetectorCommand::cmdDAC(int narg, const char * const args[], int
dac = TRIMBIT_SIZE;
else if (cmd == "vpreamp")
dac = PREAMP;
else if (cmd == "vshaper1")
else if (cmd == "vshaper1" || cmd == "vshaper")
dac = SHAPER1;
else if (cmd == "vshaper2")
else if (cmd == "vshaper2" || cmd == "vshaperneg")
dac = SHAPER2;
else if (cmd == "vhighvoltage")
dac = HIGH_VOLTAGE;
@ -3349,35 +3386,32 @@ std::string slsDetectorCommand::cmdDAC(int narg, const char * const args[], int
mode = 1;
} else if (cmd == "v_limit")
dac = V_LIMIT;
else if (cmd == "vIpre")
else if (cmd == "vipre")
dac = M_vIpre;
else if (cmd == "vIbias")
dac = M_vIbias;
else if (cmd == "vIinSh")
else if (cmd == "viinsh")
dac = M_vIinSh;
else if (cmd == "VcdSh")
else if (cmd == "vdcsh")
dac = M_VdcSh;
else if (cmd == "Vth1")
else if (cmd == "vth1")
dac = THRESHOLD;
else if (cmd == "Vth2")
else if (cmd == "vth2")
dac = M_Vth2;
else if (cmd == "Vth3")
else if (cmd == "vth3")
dac = M_Vth3;
else if (cmd == "VPL")
else if (cmd == "vpl")
dac = M_VPL;
else if (cmd == "Vtrim")
else if (cmd == "vph")
dac = CALIBRATION_PULSE;
else if (cmd == "vtrim")
dac = TRIMBIT_SIZE;
else if (cmd == "casSh")
else if (cmd == "cassh")
dac = M_casSh;
else if (cmd == "cas")
dac = M_cas;
else if (cmd == "vIcin")
else if (cmd == "vicin")
dac = M_vIcin;
else if (cmd == "vIbiasSh")
dac = M_vIbiasSh;
else if (cmd == "vIpreOut")
else if (cmd == "vipreout")
dac = M_vIpreOut;
else
return std::string("cannot decode dac ") + cmd;

2
slsSupportLib/include/sls_detector_defs.h
View File

@ -428,7 +428,6 @@ format
TEMPERATURE_FPGA2, /**< temperature sensor (fpga2 (eiger:febl) */
TEMPERATURE_FPGA3, /**< temperature sensor (fpga3 (eiger:febr) */
M_vIpre, /**< mythen 3 >*/
M_vIbias, /**< mythen 3 >*/
M_vIinSh, /**< mythen 3 >*/
M_VdcSh, /**< mythen 3 >*/
M_Vth2, /**< mythen 3 >*/
@ -436,7 +435,6 @@ format
M_Vth3, /**< mythen 3 >*/
M_casSh, /**< mythen 3 >*/
M_cas, /**< mythen 3 >*/
M_vIbiasSh, /**< mythen 3 >*/
M_vIcin, /**< mythen 3 >*/
M_vIpreOut, /**< mythen 3 >*/
V_POWER_A = 100, /**new chiptest board */

2
slsSupportLib/include/versionAPI.h
View File

@ -7,6 +7,6 @@
#define APICTB 0x190930
#define APIGOTTHARD 0x190930
#define APIJUNGFRAU 0x190930
#define APIMYTHEN3 0x190930
#define APIEIGER 0x190930
#define APIMYTHEN3 0x191004
#define APIGOTTHARD2 0x191001