mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 10:07:59 +02:00
added storage cells
This commit is contained in:
@ -392,7 +392,9 @@ void setupDetector() {
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setSpeed(CLOCK_DIVIDER, HALF_SPEED);
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cleanFifos();
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resetCore();
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configureASICTimer();
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bus_w(ADC_PORT_INVERT_REG, ADC_PORT_INVERT_VAL);
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//Initialization of acquistion parameters
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setSettings(DEFAULT_SETTINGS,-1);
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@ -411,6 +413,8 @@ void setupDetector() {
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setThresholdTemperature(DEFAULT_TMP_THRSHLD);
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// reset temp event
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setTemperatureEvent(0);
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}
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@ -434,7 +438,7 @@ int powerChip (int on){
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}
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return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_ENABLE_MSK) >> CHIP_POWER_ENABLE_OFST);
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/* temporary setup until new firmware fixes bug */
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/**temporary fix until power reg status can be read */
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//return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_STATUS_MSK) >> CHIP_POWER_STATUS_OFST);
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}
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@ -502,10 +506,9 @@ int getPhase() {
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}
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void configureASICTimer() {
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cprintf(RED," in here\n");
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//cprintf(RED,"asic reg:0x%x\n", bus_r(ASIC_CTRL_REG));
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//bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_PRCHRG_TMR_MSK) | ASIC_CTRL_PRCHRG_TMR_VAL);
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//bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | ASIC_CTRL_DS_TMR_VAL);
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printf("\nConfiguring ASIC Timer\n");
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bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_PRCHRG_TMR_MSK) | ASIC_CTRL_PRCHRG_TMR_VAL);
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bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | ASIC_CTRL_DS_TMR_VAL);
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}
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@ -644,9 +647,9 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
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case ACQUISITION_TIME:
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if(val >= 0){
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printf("\nSetting exptime: %lldns\n", (long long int)val);
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val *= (1E-3 * CLK_RUN);
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val *= (1E-3 * CLK_RUN); /*(-2)*/
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}
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retval = set64BitReg(val, SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-3 * CLK_RUN);
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retval = set64BitReg(val, SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-3 * CLK_RUN);/*(+2)*/
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printf("Getting exptime: %lldns\n", (long long int)retval);
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break;
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@ -675,6 +678,16 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
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printf("Getting #cycles: %lld\n", (long long int)retval);
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break;
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case STORAGE_CELL_NUMBER:
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if(val >= 0) {
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printf("\nSetting #storage cells to %lld\n", (long long int)val);
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bus_w(CONTROL_REG, (bus_r(CONTROL_REG) & ~CONTROL_STORAGE_CELL_NUM_MSK) |
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((val << CONTROL_STORAGE_CELL_NUM_OFST) & CONTROL_STORAGE_CELL_NUM_MSK));
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}
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retval = ((bus_r(CONTROL_REG) & CONTROL_STORAGE_CELL_NUM_MSK) >> CONTROL_STORAGE_CELL_NUM_OFST);
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printf("Getting #storage cells: %lld\n", (long long int)retval);
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break;
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default:
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cprintf(RED,"Warning: Timer Index not implemented for this detector: %d\n", ind);
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break;
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@ -93,16 +93,18 @@ enum NETWORKINDEX { TXN_FRAME };
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#define ADC_PORT_INVERT_VAL (0x453b2a9c)
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#define MAX_TIMESLOT_VAL (0x1F)
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#define MAX_THRESHOLD_TEMP_VAL (127999) //millidegrees
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#define MAX_STORAGE_CELL_VAL (15) //0xF
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#define SAMPLE_ADC_HALF_SPEED (SAMPLE_DECMT_FACTOR_2_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x1000 */
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#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_DECMT_FACTOR_4_VAL + SAMPLE_DGTL_SAMPLE_8_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x2810 */
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#define CONFIG_HALF_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
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#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
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#define ADC_OFST_HALF_SPEED_VAL (0x20) //adc pipeline
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#define ADC_OFST_QUARTER_SPEED_VAL (0x0f)
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#define ADC_PHASE_HALF_SPEED (0x48) //72
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#define ADC_PHASE_QUARTER_SPEED (0x48) //72
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#define ADC_OFST_HALF_SPEED_VAL (0x1f) //(0x20)
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#define ADC_OFST_QUARTER_SPEED_VAL (0x0f) //(0x0f)
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#define ADC_PHASE_HALF_SPEED (0x2D) //45
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#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
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#define ADC_PORT_INVERT_VAL (0x453b2a9c)
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/* Maybe not required for jungfrau */
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#define NTRIMBITS (6)
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