added storage cells

This commit is contained in:
2018-04-13 15:05:43 +02:00
parent bdcccb7732
commit e024774323
14 changed files with 218 additions and 56 deletions

View File

@ -392,7 +392,9 @@ void setupDetector() {
setSpeed(CLOCK_DIVIDER, HALF_SPEED);
cleanFifos();
resetCore();
configureASICTimer();
bus_w(ADC_PORT_INVERT_REG, ADC_PORT_INVERT_VAL);
//Initialization of acquistion parameters
setSettings(DEFAULT_SETTINGS,-1);
@ -411,6 +413,8 @@ void setupDetector() {
setThresholdTemperature(DEFAULT_TMP_THRSHLD);
// reset temp event
setTemperatureEvent(0);
}
@ -434,7 +438,7 @@ int powerChip (int on){
}
return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_ENABLE_MSK) >> CHIP_POWER_ENABLE_OFST);
/* temporary setup until new firmware fixes bug */
/**temporary fix until power reg status can be read */
//return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_STATUS_MSK) >> CHIP_POWER_STATUS_OFST);
}
@ -502,10 +506,9 @@ int getPhase() {
}
void configureASICTimer() {
cprintf(RED," in here\n");
//cprintf(RED,"asic reg:0x%x\n", bus_r(ASIC_CTRL_REG));
//bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_PRCHRG_TMR_MSK) | ASIC_CTRL_PRCHRG_TMR_VAL);
//bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | ASIC_CTRL_DS_TMR_VAL);
printf("\nConfiguring ASIC Timer\n");
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_PRCHRG_TMR_MSK) | ASIC_CTRL_PRCHRG_TMR_VAL);
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | ASIC_CTRL_DS_TMR_VAL);
}
@ -644,9 +647,9 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
case ACQUISITION_TIME:
if(val >= 0){
printf("\nSetting exptime: %lldns\n", (long long int)val);
val *= (1E-3 * CLK_RUN);
val *= (1E-3 * CLK_RUN); /*(-2)*/
}
retval = set64BitReg(val, SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-3 * CLK_RUN);
retval = set64BitReg(val, SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-3 * CLK_RUN);/*(+2)*/
printf("Getting exptime: %lldns\n", (long long int)retval);
break;
@ -675,6 +678,16 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
printf("Getting #cycles: %lld\n", (long long int)retval);
break;
case STORAGE_CELL_NUMBER:
if(val >= 0) {
printf("\nSetting #storage cells to %lld\n", (long long int)val);
bus_w(CONTROL_REG, (bus_r(CONTROL_REG) & ~CONTROL_STORAGE_CELL_NUM_MSK) |
((val << CONTROL_STORAGE_CELL_NUM_OFST) & CONTROL_STORAGE_CELL_NUM_MSK));
}
retval = ((bus_r(CONTROL_REG) & CONTROL_STORAGE_CELL_NUM_MSK) >> CONTROL_STORAGE_CELL_NUM_OFST);
printf("Getting #storage cells: %lld\n", (long long int)retval);
break;
default:
cprintf(RED,"Warning: Timer Index not implemented for this detector: %d\n", ind);
break;

View File

@ -93,16 +93,18 @@ enum NETWORKINDEX { TXN_FRAME };
#define ADC_PORT_INVERT_VAL (0x453b2a9c)
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) //millidegrees
#define MAX_STORAGE_CELL_VAL (15) //0xF
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_DECMT_FACTOR_2_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x1000 */
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_DECMT_FACTOR_4_VAL + SAMPLE_DGTL_SAMPLE_8_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x2810 */
#define CONFIG_HALF_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
#define ADC_OFST_HALF_SPEED_VAL (0x20) //adc pipeline
#define ADC_OFST_QUARTER_SPEED_VAL (0x0f)
#define ADC_PHASE_HALF_SPEED (0x48) //72
#define ADC_PHASE_QUARTER_SPEED (0x48) //72
#define ADC_OFST_HALF_SPEED_VAL (0x1f) //(0x20)
#define ADC_OFST_QUARTER_SPEED_VAL (0x0f) //(0x0f)
#define ADC_PHASE_HALF_SPEED (0x2D) //45
#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
#define ADC_PORT_INVERT_VAL (0x453b2a9c)
/* Maybe not required for jungfrau */
#define NTRIMBITS (6)