diff --git a/python/tests/test_det_api.py b/python/tests/test_det_api.py
index 6db456a34..0cd5ff4be 100644
--- a/python/tests/test_det_api.py
+++ b/python/tests/test_det_api.py
@@ -394,3 +394,168 @@ def test_patternstart(session_simulator, request):
         assert "not implemented" in str(exc_info.value)
 
     Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+
+
+@pytest.mark.detectorintegration
+def test_runclk(session_simulator, request):
+    """ Test using runclk for ctb and xilinx_ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    from slsdet import Hz, MHz, kHz
+
+    if det_type in ['ctb', 'xilinx_ctb']:
+        prev_runclk = d.getRUNClock()
+
+        d.runclk
+
+        # invalid value type
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = 5e6
+
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = 5 * 1000 * 1000
+
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = Hz(5e6)
+
+        d.runclk = MHz(5)
+        assert d.runclk.value == 5_000_000
+
+        d.runclk = MHz(4.5)
+        assert d.runclk.value == 4_500_000
+
+        d.runclk = kHz(5000.5)
+        assert d.runclk.value == 5_000_500
+
+        # invalid values from server
+        # max is 300MHz
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = MHz(301)
+
+        # min is 2MHz for ctb and 10MHz for xilinx_ctb
+        if det_type == 'ctb':
+            with pytest.raises(Exception) as exc_info:
+                d.runclk = MHz(1)
+        else:
+            with pytest.raises(Exception) as exc_info:
+                d.runclk = MHz(9)
+
+        for i in range(len(d)):
+            d.setRUNClock(prev_runclk[i], [i])
+
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+@pytest.mark.detectorintegration
+def test_adcclk(session_simulator, request):
+    """ Test using adcclk for ctb and xilinx_ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    from slsdet import Hz, MHz, kHz
+
+    if det_type in ['ctb', 'xilinx_ctb']:
+        prev_adcclk = d.getADCClock()
+
+        d.adcclk
+
+        # invalid value type
+        with pytest.raises(Exception) as exc_info:
+            d.adcclk = 5e6
+
+        with pytest.raises(Exception) as exc_info:
+            d.adcclk = 5 * 1000 * 1000
+
+        with pytest.raises(Exception) as exc_info:
+            d.adcclk = Hz(5e6)
+
+        d.adcclk = MHz(5)
+        assert d.adcclk.value == 5_000_000
+
+        d.adcclk = MHz(4.5)
+        assert d.adcclk.value == 4_500_000
+
+        d.adcclk = kHz(5000.5)
+        assert d.adcclk.value == 5_000_500
+
+        # invalid values from server
+        # max is 300MHz
+        with pytest.raises(Exception) as exc_info:
+            d.adcclk = MHz(301)
+
+        # min is 2MHz for ctb and 10MHz for xilinx_ctb
+        if det_type == 'ctb':
+            with pytest.raises(Exception) as exc_info:
+                d.adcclk = MHz(1)
+        else:
+            with pytest.raises(Exception) as exc_info:
+                d.adcclk = MHz(9)
+
+        for i in range(len(d)):
+            d.setADCClock(prev_adcclk[i], [i])
+
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+
+@pytest.mark.detectorintegration
+def test_dbitclk(session_simulator, request):
+    """ Test using dbitclk for ctb and xilinx_ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    from slsdet import Hz, MHz, kHz
+
+    if det_type in ['ctb', 'xilinx_ctb']:
+        prev_dbitclk = d.getDBITClock()
+
+        d.dbitclk
+
+        # invalid value type
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = 5e6
+
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = 5 * 1000 * 1000
+
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = Hz(5e6)
+
+        d.dbitclk = MHz(5)
+        assert d.dbitclk.value == 5_000_000
+
+        d.dbitclk = MHz(4.5)
+        assert d.dbitclk.value == 4_500_000
+
+        d.dbitclk = kHz(5000.5)
+        assert d.dbitclk.value == 5_000_500
+
+        # invalid values from server
+        # max is 300MHz
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = MHz(301)
+
+        # min is 2MHz for ctb and 10MHz for xilinx_ctb
+        if det_type == 'ctb':
+            with pytest.raises(Exception) as exc_info:
+                d.dbitclk = MHz(1)
+        else:
+            with pytest.raises(Exception) as exc_info:
+                d.dbitclk = MHz(9)
+
+        for i in range(len(d)):
+            d.setDBITClock(prev_dbitclk[i], [i])
+
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+
+@pytest.mark.detectorintegration
+def test_syncclk(session_simulator, request):
+    """ Test using syncclk for ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    if det_type in ['ctb']:
+        d.syncclk
+
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
\ No newline at end of file
diff --git a/python/tests/test_freq.py b/python/tests/test_freq.py
index a4cb47127..c065aa31d 100644
--- a/python/tests/test_freq.py
+++ b/python/tests/test_freq.py
@@ -1,14 +1,20 @@
-from slsdet import Hz
-'''
+from slsdet import Hz, MHz, kHz
+
 def test_Hz():
     f = Hz(1)
-    assert f.value() == 1e6
-    f = Hz('1MHz')
-    assert f.value() == 1e6
-    f = Hz('5000kHz')
-    assert f.value() == 5e6
-    assert Hz(1) == 1
-    assert Hz(1e6) == 1e6
-    assert Hz(1, 'MHz') == 1e6
-    assert Hz(0.5, 'GHz') == 0.5e9
-'''
\ No newline at end of file
+    assert f.value == 1
+    f = Hz(1 * 1000)
+    assert f.value == 1000
+    f = MHz(5)
+    assert f.value == 5_000_000
+    f = MHz(0.5)
+    assert f.value == 500_000
+    f = kHz(2.5)
+    assert f.value == 2500
+    f = kHz(5000)
+    assert f.value == 5_000_000
+
+def test_rounding_exact():
+    f = MHz(1.234)
+    assert f.value == round(1.234 * 1_000_000)
+