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gotthard2, change clock, remember in degrees, and max clock divider is 512

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This commit is contained in:
maliakal_d 2019-10-17 18:29:57 +02:00
parent e16212bd23
commit df4f37efc6
3 changed files with 7 additions and 9 deletions
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BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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14
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -789,13 +789,13 @@ int setClockDivider(enum CLKINDEX ind, int val) {
FILE_LOG(logINFO, ("\tConfiguring Click Divider of C%d(%s) from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", ind, clock_names[ind], currentdiv, clkDivider[ind], val, newfreq, vcofreq)); FILE_LOG(logINFO, ("\tConfiguring Click Divider of C%d(%s) from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", ind, clock_names[ind], currentdiv, clkDivider[ind], val, newfreq, vcofreq));
// Remembering old phases // Remembering old phases in degrees
int oldPhases[NUM_CLOCKS]; int oldPhases[NUM_CLOCKS];
{ {
int i = 0; int i = 0;
for (i = 0; i < NUM_CLOCKS; ++i) { for (i = 0; i < NUM_CLOCKS; ++i) {
oldPhases [i] = getPhase(i, 0); oldPhases [i] = getPhase(i, 1);
FILE_LOG(logDEBUG1, ("\tRemembering C%d (%s) phase: %d\n", ind, clock_names, oldPhases[i])); FILE_LOG(logDEBUG1, ("\tRemembering C%d (%s) phase: %d degrees\n", ind, clock_names, oldPhases[i]));
} }
} }
@ -817,14 +817,12 @@ int setClockDivider(enum CLKINDEX ind, int val) {
clkPhase[SYSTEM_C3] = 0; clkPhase[SYSTEM_C3] = 0;
} }
// set the phase if custom set // set the phase in degreesif custom set
{ {
int i = 0; int i = 0;
for (i = 0; i < NUM_CLOCKS; ++i) { for (i = 0; i < NUM_CLOCKS; ++i) {
if (clkPhase[i] != oldPhases[i]) { FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting C%d(%s) to %d degrees\n", i, clock_names[i], oldPhases[i]));
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting C%d(%s) to %d\n", i, clock_names[i], oldPhases[i])); setPhase(i, oldPhases[i], 1);
setPhase(i, oldPhases[i], 0);
}
} }
} }
return ret; return ret;

2
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c
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@ -14,7 +14,7 @@
// c counter (C0-C8 (+1 to base address)) // c counter (C0-C8 (+1 to base address))
#define ALTERA_PLL_C10_C_COUNTER_BASE_REG (0x0C0) #define ALTERA_PLL_C10_C_COUNTER_BASE_REG (0x0C0)
#define ALTERA_PLL_C10_C_COUNTER_MAX_DIVIDER_VAL (0xFF) #define ALTERA_PLL_C10_C_COUNTER_MAX_DIVIDER_VAL (512)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST (0) #define ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST) #define ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST (8) #define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST (8)