detectors/slsDetectorPackage
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merge from 7.0.0

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This commit is contained in:
maliakal_d
2023-02-24 10:39:51 +01:00
parent 48a684b95f e942678139
commit dc5db905d4
101 changed files with 4009 additions and 2128 deletions
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BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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10
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -89,7 +89,7 @@ void basictests() {
#endif
if (mapCSP0() == FAIL) {
strcpy(initErrorMessage,
"Could not map to memory. Dangerous to continue.\n");
"Could not map to memory. Cannot proceed. Check Firmware.\n");
LOG(logERROR, (initErrorMessage));
initError = FAIL;
}
@ -99,8 +99,10 @@ void basictests() {
((validateKernelVersion(KERNEL_DATE_VRSN) == FAIL) ||
(checkType() == FAIL) || (testFpga() == FAIL) ||
(testBus() == FAIL))) {
strcpy(initErrorMessage, "Could not pass basic tests of FPGA and bus. "
"Dangerous to continue.\n");
sprintf(initErrorMessage,
"Could not pass basic tests of FPGA and bus. Cannot proceed. "
"Check Firmware. (Firmware version:0x%llx) \n",
getFirmwareVersion());
LOG(logERROR, ("%s\n\n", initErrorMessage));
initError = FAIL;
return;
@ -388,7 +390,7 @@ void initStopServer() {
if (mapCSP0() == FAIL) {
initError = FAIL;
strcpy(initErrorMessage,
"Stop Server: Map Fail. Dangerous to continue. Goodbye!\n");
"Stop Server: Map Fail. Cannot proceed. Check Firmware. \n");
LOG(logERROR, (initErrorMessage));
initCheckDone = 1;
return;

10
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -3,7 +3,7 @@
#pragma once
#include "sls/sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN (0x221205)
#define REQRD_FRMWRE_VRSN (0x230124)
#define KERNEL_DATE_VRSN "Mon May 10 18:00:21 CEST 2021"
#define ID_FILE "detid_mythen3.txt"
@ -57,10 +57,10 @@
#define DEFAULT_TRIMBIT_VALUE (0)
#define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
#define DEFAULT_READOUT_C0 (12) //(083333333) // rdo_clk, 83.33 MHz
#define DEFAULT_READOUT_C1 (12) //(083333333) // rdo_smp_clk, 83.33 MHz
#define DEFAULT_SYSTEM_C0 (20) //(050000000) // run_clk, 20 MHz
#define DEFAULT_SYSTEM_C1 (8) //(125000000) // str_clk, 125 MHz const
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // rdo_smp_clk, 100 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (6) //(166666666) // str_clk, 166 MHz const
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz