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This commit is contained in:
maliakal_d
2021-07-22 11:15:57 +02:00
parent fd6e44c396 206c48c7a0
commit da996314e7
28 changed files with 655 additions and 116 deletions
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20
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
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@ -34,6 +34,10 @@
#define BASE_FLOW_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/f37608230b4721661f29aacc20124555705ee705/flow/flow_ctrl.vhd
/** Veto processing core */
#define BASE_VETO_PRCSSNG (0x0300) // 0x1806_0300 - 0x1806_03FF?
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/veto/veto_ctrl.vhd
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
@ -86,7 +90,9 @@
#define CONFIG_VETO_ENBL_OFST (0)
#define CONFIG_VETO_ENBL_MSK (0x00000001 << CONFIG_VETO_ENBL_OFST)
#define CONFIG_VETO_CH_10GB_ENBL_OFST (1)
#define CONFIG_VETO_CH_3GB_ENBL_OFST (11)
#define CONFIG_VETO_CH_3GB_ENBL_MSK (0x00000001 << CONFIG_VETO_CH_3GB_ENBL_OFST)
#define CONFIG_VETO_CH_10GB_ENBL_OFST (15)
#define CONFIG_VETO_CH_10GB_ENBL_MSK (0x00000001 << CONFIG_VETO_CH_10GB_ENBL_OFST)
/* Control RW register */
@ -110,10 +116,6 @@
/** DTA Offset Register */
#define DTA_OFFSET_REG (0x0A * REG_OFFSET + BASE_CONTROL)
/** Mask Strip Registers (40) */
#define MASK_STRIP_START_REG (0x18 * REG_OFFSET + BASE_CONTROL)
#define MASK_STRIP_NUM_REGS (40)
/* ASIC registers --------------------------------------------------*/
/* ASIC Config register */
@ -258,4 +260,10 @@
#define RXR_ENDPOINTS_MAX (32)
#define RXR_ENDPOINT_OFST (16 * REG_OFFSET)
// clang-format on
/** Veto processing core --------------------------------------------------*/
/** Mask Strip Registers (40) */
#define MASK_STRIP_START_REG (0x00 * REG_OFFSET + BASE_VETO_PRCSSNG)
#define MASK_STRIP_NUM_REGS (40)
// clang-format on

35
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -989,7 +989,7 @@ int setExpTime(int64_t val) {
return FAIL;
}
LOG(logINFO, ("Setting exptime %lld ns\n", val));
val *= (1E-9 * systemFrequency);
val = (val * 1E-9 * systemFrequency) + 0.5;
set64BitReg(val, ASIC_INT_EXPTIME_LSB_REG, ASIC_INT_EXPTIME_MSB_REG);
// validate for tolerance
@ -1014,7 +1014,7 @@ int setPeriod(int64_t val) {
// continuous
if (burstMode == CONTINUOUS_INTERNAL || burstMode == CONTINUOUS_EXTERNAL) {
LOG(logINFO, ("Setting period %lld ns [Continuous mode]\n", val));
val *= (1E-9 * systemFrequency);
val = (val * 1E-9 * systemFrequency) + 0.5;
// trigger
if (getTiming() == TRIGGER_EXPOSURE) {
LOG(logINFO,
@ -1029,7 +1029,7 @@ int setPeriod(int64_t val) {
// burst
else {
LOG(logINFO, ("Setting period %lld ns [Burst mode]\n", val));
val *= (1E-9 * systemFrequency);
val = (val * 1E-9 * systemFrequency) + 0.5;
set64BitReg(val, ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG);
}
periodReg = val;
@ -1067,7 +1067,7 @@ int setDelayAfterTrigger(int64_t val) {
return FAIL;
}
LOG(logINFO, ("Setting delay after trigger %lld ns\n", val));
val *= (1E-9 * systemFrequency);
val = (val * 1E-9 * systemFrequency) + 0.5;
delayReg = val;
if (getTiming() == AUTO_TIMING) {
LOG(logINFO, ("\tAuto mode (not writing to register)\n"));
@ -1097,7 +1097,7 @@ int setBurstPeriod(int64_t val) {
return FAIL;
}
LOG(logINFO, ("Setting burst period %lld ns\n", val));
val *= (1E-9 * systemFrequency);
val = (val * 1E-9 * systemFrequency) + 0.5;
burstPeriodReg = val;
// burst and auto
@ -1581,14 +1581,14 @@ enum timingMode getTiming() {
void setNumberofUDPInterfaces(int val) {
uint32_t addr = CONFIG_REG;
// 2 interfaces (enable veto)
// 2 rxr interfaces (enable debugging interface)
if (val > 1) {
LOG(logINFOBLUE, ("Setting #Interfaces: 2 (10gbps veto streaming)\n"));
LOG(logINFOBLUE, ("Enabling 10GbE (debugging) veto streaming\n"));
bus_w(addr, bus_r(addr) | CONFIG_VETO_CH_10GB_ENBL_MSK);
}
// 1 interface (disable veto)
// 1 rxr interface (disable debugging interface)
else {
LOG(logINFOBLUE, ("Setting #Interfaces: 1 (2.5gbps veto streaming)\n"));
LOG(logINFOBLUE, ("Disabling 10GbE (debugging) veto streaming\n"));
bus_w(addr, bus_r(addr) & ~CONFIG_VETO_CH_10GB_ENBL_MSK);
}
LOG(logDEBUG, ("config reg:0x%x\n", bus_r(addr)));
@ -2578,6 +2578,23 @@ int getVeto() {
CONFIG_VETO_ENBL_OFST);
}
void setVetoStream(int value) {
uint32_t addr = CONFIG_REG;
if (value) {
LOG(logINFOBLUE, ("Enabling 3GbE veto streaming\n"));
bus_w(addr, bus_r(addr) | CONFIG_VETO_CH_3GB_ENBL_MSK);
} else {
LOG(logINFOBLUE, ("Disabling 3GbE veto streaming\n"));
bus_w(addr, bus_r(addr) & ~CONFIG_VETO_CH_3GB_ENBL_MSK);
}
LOG(logDEBUG, ("config reg:0x%x\n", bus_r(addr)));
}
int getVetoStream() {
return ((bus_r(CONFIG_REG) & CONFIG_VETO_CH_3GB_ENBL_MSK) ? 1 : 0);
}
void setBadChannels(int nch, int *channels) {
LOG(logINFO, ("Setting %d bad channels\n", nch));

2
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
View File

@ -1,7 +1,7 @@
#pragma once
#include "sls/sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN (0x200925)
#define REQRD_FRMWRE_VRSN (0x210527)
#define KERNEL_DATE_VRSN "Wed May 20 13:58:38 CEST 2020"
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)