eiger server: interrupt subframe, quad change flipping, registers set left and right separately

This commit is contained in:
2019-07-29 15:19:46 +02:00
parent 58e6338f9c
commit d981e1b8e5
18 changed files with 325 additions and 54 deletions

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@ -1214,6 +1214,7 @@ void Beb_SetDetectorNumber(uint32_t detid) {
int Beb_SetQuad(int val) {
if (val >= 0) {
printf("Setting Quad to %d in Beb\n", val);
Beb_quadEnable = (val == 0 ? 0 : 1);
Beb_SetDetectorPosition(Beb_positions);
}

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@ -2009,64 +2009,165 @@ int Feb_Control_SoftwareTrigger() {
return 1;
}
int Feb_Control_InterruptSubframe(int val) {
if (val >= 0) {
printf("Setting Interrupt Subframe to %d\n", val);
}
// they need to be written separately because the left and right registers have different values for this particular register
uint32_t offset = DAQ_REG_HRDWRE;
int top = Module_TopAddressIsValid(&modules[1]) ? 1 : 0;
uint32_t lvalue = 0;
uint32_t rvalue = 0;
// right
unsigned int addr = top ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
if (val >= 0) {
if(!Feb_Interface_ReadRegister(addr, offset, &rvalue)) {
cprintf(RED,"Could not read %s right interrupt subframe\n", top ? "top" : "bottom");
return -1;
}
uint32_t data = ((val == 0) ? (rvalue &~ DAQ_REG_HRDWRE_INTRRPT_SF_MSK) : (rvalue | DAQ_REG_HRDWRE_INTRRPT_SF_MSK));
if(!Feb_Interface_WriteRegister(addr, offset, data, 0, 0)) {
cprintf(RED,"Could not write 0x%x to %s right interrupt subframe addr 0x%x\n", data, top ? "top" : "bottom", offset);
return -1;
}
}
if(!Feb_Interface_ReadRegister(addr, offset, &rvalue)) {
cprintf(RED,"Could not read back %s right interrupt subframe\n", top ? "top" : "bottom");
return -1;
}
// left
addr = top ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
if (val >= 0) {
if(!Feb_Interface_ReadRegister(addr, offset, &lvalue)) {
cprintf(RED,"Could not read %s left interrupt subframe\n", top ? "top" : "bottom");
return -1;
}
uint32_t data = ((val == 0) ? (lvalue &~ DAQ_REG_HRDWRE_INTRRPT_SF_MSK) : (lvalue | DAQ_REG_HRDWRE_INTRRPT_SF_MSK));
if(!Feb_Interface_WriteRegister(addr, offset, data, 0, 0)) {
cprintf(RED,"Could not write 0x%x to %s left interrupt subframe addr 0x%x\n", data, top ? "top" : "bottom", offset);
return -1;
}
}
if(!Feb_Interface_ReadRegister(addr, offset, &lvalue)) {
cprintf(RED,"Could not read back %s left interrupt subframe\n", top ? "top" : "bottom");
return -1;
}
// inconsistent
if (lvalue != rvalue) {
cprintf(RED, "Inconsistent values of interrupt subframe betweeen left and right\n");
return -1;
}
return (lvalue & DAQ_REG_HRDWRE_INTRRPT_SF_MSK) >> DAQ_REG_HRDWRE_INTRRPT_SF_OFST;
}
int Feb_Control_SetQuad(int val) {
// no bottom for quad
if (!Module_TopAddressIsValid(&modules[1])) {
return 0;
}
uint32_t offset = DAQ_REG_HRDWRE;
if (val >= 0) {
printf("Setting Quad to %d in Feb\n", val);
unsigned int addr = Module_GetTopRightAddress (&modules[1]);
uint32_t rvalue = 0;
if(!Feb_Interface_ReadRegister(addr, offset, &rvalue)) {
cprintf(RED,"Could not read top right quad reg\n");
return -1;
}
uint32_t data = ((val == 0) ? (rvalue &~ DAQ_REG_HRDWRE_OW_MSK) : ((rvalue | DAQ_REG_HRDWRE_OW_MSK) &~ DAQ_REG_HRDWRE_TOP_MSK));
if(!Feb_Interface_WriteRegister(addr, offset, data, 0, 0)) {
cprintf(RED,"Could not write 0x%x to top right quad addr 0x%x\n", data, offset);
return -1;
}
}
return 0;
}
uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
uint32_t value=0;
if(Module_TopAddressIsValid(&modules[1])){
if(!Feb_Interface_WriteRegister(Module_GetTopRightAddress (&modules[1]),offset, data,0, 0)) {
cprintf(RED,"Could not read tr value. Value read:%d\n", value);
value = 0;
}
if(!Feb_Interface_WriteRegister(Module_GetTopLeftAddress (&modules[1]),offset, data,0, 0)) {
cprintf(RED,"Could not read tl value. Value read:%d\n", value);
value = 0;
}
uint32_t actualOffset = offset;
int left = 0;
int right = 0;
// both registers
if (offset < 0x100) {
left = 1;
right = 1;
}
// right registers only
else if (offset >= 0x200) {
right = 1;
actualOffset = offset - 0x200;
} else {
if(!Feb_Interface_WriteRegister(Module_GetBottomRightAddress (&modules[1]),offset, data,0, 0)) {
cprintf(RED,"Could not read br value. Value read:%d\n", value);
value = 0;
}
if(!Feb_Interface_WriteRegister(Module_GetBottomLeftAddress (&modules[1]),offset, data,0, 0)) {
cprintf(RED,"Could not read bl value. Value read:%d\n", value);
value = 0;
}
left = 1;
actualOffset = offset - 0x100;
}
int top = Module_TopAddressIsValid(&modules[1]) ? 1 : 0;
unsigned int addr = top ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
if (right) {
if(!Feb_Interface_WriteRegister(addr,actualOffset, data,0, 0)) {
cprintf(RED,"Could not write 0x%x to %s right addr 0x%x\n", data, top ? "top" : "bottom", actualOffset);
}
}
addr = top ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
if (left) {
if(!Feb_Interface_WriteRegister(addr,actualOffset, data,0, 0)) {
cprintf(RED,"Could not write 0x%x to %s left addr 0x%x\n", data, top ? "top" : "bottom", actualOffset);
}
}
return Feb_Control_ReadRegister(offset);
}
uint32_t Feb_Control_ReadRegister(uint32_t offset) {
uint32_t value=0;
uint32_t value1=0;
if(Module_TopAddressIsValid(&modules[1])){
if(!Feb_Interface_ReadRegister(Module_GetTopRightAddress (&modules[1]),offset, &value)) {
cprintf(RED,"Could not read value. Value read:%d\n", value);
value = 0;
}
printf("Read top right addr: 0x%08x\n", value);
if(!Feb_Interface_ReadRegister(Module_GetTopLeftAddress (&modules[1]),offset, &value1)) {
cprintf(RED,"Could not read value. Value read:%d\n", value1);
value1 = 0;
}
printf("Read top left addr: 0x%08x\n", value1);
if (value != value1)
value = -1;
uint32_t actualOffset = offset;
int left = 0;
int right = 0;
// both registers
if (offset < 0x100) {
left = 1;
right = 1;
}
// right registers only
else if (offset >= 0x200) {
right = 1;
actualOffset = offset - 0x200;
} else {
if(!Feb_Interface_ReadRegister(Module_GetBottomRightAddress (&modules[1]),offset, &value)) {
cprintf(RED,"Could not read value. Value read:%d\n", value);
value = 0;
}
printf("Read bottom right addr: 0x%08x\n", value);
if(!Feb_Interface_ReadRegister(Module_GetBottomLeftAddress (&modules[1]),offset, &value1)) {
cprintf(RED,"Could not read value. Value read:%d\n", value1);
value1 = 0;
}
printf("Read bottom left addr: 0x%08x\n", value1);
if (value != value1)
value = -1;
left = 1;
actualOffset = offset - 0x100;
}
return value;
uint32_t lvalue=0;
uint32_t rvalue=0;
int top = Module_TopAddressIsValid(&modules[1]) ? 1 : 0;
unsigned int addr = top ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
if (right) {
if(!Feb_Interface_ReadRegister(addr, actualOffset, &rvalue)) {
cprintf(RED,"Could not read %s right addr 0x%x\n", top ? "top" : "bottom", actualOffset);
return -1;
}
printf("Read %s right addr: 0x%08x\n", top ? "top" : "bottom", rvalue);
if (!left) {
return rvalue;
}
}
addr = top ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
if(left) {
if(!Feb_Interface_ReadRegister(addr, actualOffset, &lvalue)) {
cprintf(RED,"Could not read %s left addr 0x%x\n", top ? "top" : "bottom", actualOffset);
return -1;
}
printf("Read %s left addr: 0x%08x\n", top ? "top" : "bottom", lvalue);
if (!right) {
return lvalue;
}
}
if (lvalue != rvalue) {
cprintf(RED, "Inconsistent values betweeen left and right\n");
return -1;
}
return lvalue;
}

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@ -204,6 +204,8 @@ int Feb_Control_GetModuleNumber();
int64_t Feb_Control_GetSubMeasuredPeriod();
int Feb_Control_SoftwareTrigger();
int Feb_Control_InterruptSubframe(int val);
int Feb_Control_SetQuad(int val);
uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
uint32_t Feb_Control_ReadRegister(uint32_t offset);

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@ -20,6 +20,14 @@
#define DAQ_REG_SUBFRAME_EXPOSURES 6
#define DAQ_REG_SUBFRAME_PERIOD 7 //also pg and fifo status register
#define DAQ_REG_HRDWRE 12
#define DAQ_REG_HRDWRE_OW_OFST (0)
#define DAQ_REG_HRDWRE_OW_MSK (0x00000001 << DAQ_REG_HRDWRE_OW_OFST)
#define DAQ_REG_HRDWRE_TOP_OFST (1)
#define DAQ_REG_HRDWRE_TOP_MSK (0x00000001 << DAQ_REG_HRDWRE_TOP_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_OFST (3)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK (0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_RO_OFFSET 20
#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
@ -29,6 +37,7 @@
#define DAQ_CTRL_RESET 0x80000000
#define DAQ_CTRL_START 0x40000000
#define ACQ_CTRL_START 0x50000000 //this is 0x10000000 (acq) | 0x40000000 (daq)

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@ -1220,7 +1220,14 @@ int setDetectorPosition(int pos[]) {
int setQuad(int val) {
return Beb_SetQuad(val);
int ret = Beb_SetQuad(val);
if (Feb_Control_SetQuad(val) == -1)
return -1;
return ret;
}
int setInterruptSubframe(int val) {
return Feb_Control_InterruptSubframe(val);
}