From d7eaa4d4d9e017be8c8602159cd09dbc58a8cce1 Mon Sep 17 00:00:00 2001 From: lrlunin Date: Fri, 10 Jul 2026 11:57:50 +0200 Subject: [PATCH] fix image references, filename in index --- docs/src/index.rst | 2 +- docs/src/softwarearchitecture.rst | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/docs/src/index.rst b/docs/src/index.rst index 498543384..8a5044cea 100644 --- a/docs/src/index.rst +++ b/docs/src/index.rst @@ -52,7 +52,7 @@ slsDetectorPackage pyenums pypower pyexamples - pyPatternGenerator + pypatterngenerator pattern .. toctree:: diff --git a/docs/src/softwarearchitecture.rst b/docs/src/softwarearchitecture.rst index 97145e0fe..8638924b1 100644 --- a/docs/src/softwarearchitecture.rst +++ b/docs/src/softwarearchitecture.rst @@ -7,8 +7,8 @@ Software Architecture Introduction ------------------------------------ -.. figure:: images/System_communication_architecture.png - :target: _images/System_communication_architecture.png +.. figure:: images/System_communication_architecture.svg + :target: _images/System_communication_architecture.svg :width: 700px :align: center :alt: System communication architecture @@ -46,8 +46,8 @@ Next, each component is examined in detail. Module ------- -.. figure:: images/Module_architecture.png - :target: _images/Module_architecture.png +.. figure:: images/Module_architecture.svg + :target: _images/Module_architecture.svg :width: 700px :align: center :alt: Module architecture @@ -66,8 +66,8 @@ The module also includes an FPGA with VHDL firmware (file format depends on the Upgrade ^^^^^^^^ -.. figure:: images/Soft_upgrade_components.png - :target: _images/Soft_upgrade_components.png +.. figure:: images/Soft_upgrade_components.svg + :target: _images/Soft_upgrade_components.svg :width: 700px :align: center :alt: Software Upgrade Components @@ -97,8 +97,8 @@ When only updating the detector server, use the `updatedetectorserver command