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eiger server: quad, interrupt subframe, reg left and right (#45)
* eiger server: quad, interrupt subframe, reg left and right * eiger server: beb can fail in setting up quad, quad and gap pixels
This commit is contained in:

committed by
Erik Fröjdh

parent
e17de0609c
commit
d72b6c3659
@ -2014,61 +2014,171 @@ int Feb_Control_SoftwareTrigger() {
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return 1;
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}
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int Feb_Control_SetInterruptSubframe(int val) {
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FILE_LOG(logINFO, ("Setting Interrupt Subframe to %d\n", val));
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uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
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uint32_t value=0;
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if (Module_TopAddressIsValid(&modules[1])) {
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if (!Feb_Interface_WriteRegister(Module_GetTopRightAddress (&modules[1]),offset, data,0, 0)) {
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FILE_LOG(logERROR, ("Could not read tr value. Value read:%d\n", value));
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value = 0;
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// they need to be written separately because the left and right registers have different values for this particular register
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uint32_t offset = DAQ_REG_HRDWRE;
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uint32_t regVal = 0;
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char side[2][10] = {"right", "left"};
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char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
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unsigned int addr[2];
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addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
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addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
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int iloop = 0;
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for(iloop = 0; iloop < 2; ++iloop) {
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// get previous value to keep it
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if(!Feb_Interface_ReadRegister(addr[iloop], offset, ®Val)) {
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FILE_LOG(logERROR, ("Could not read %s %s interrupt subframe\n", isTop, side[iloop]));
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return 0;
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}
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if(!Feb_Interface_WriteRegister(Module_GetTopLeftAddress (&modules[1]),offset, data,0, 0)) {
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FILE_LOG(logERROR, ("Could not read tl value. Value read:%d\n", value));
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value = 0;
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}
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} else {
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if (!Feb_Interface_WriteRegister(Module_GetBottomRightAddress (&modules[1]),offset, data,0, 0)) {
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FILE_LOG(logERROR, ("Could not read br value. Value read:%d\n", value));
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value = 0;
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uint32_t data = ((val == 0) ? (regVal &~ DAQ_REG_HRDWRE_INTRRPT_SF_MSK) : (regVal | DAQ_REG_HRDWRE_INTRRPT_SF_MSK));
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if(!Feb_Interface_WriteRegister(addr[iloop], offset, data, 0, 0)) {
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FILE_LOG(logERROR, ("Could not write 0x%x to %s %s interrupt subframe addr 0x%x\n", data, isTop, side[iloop], offset));
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return 0;
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}
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if(!Feb_Interface_WriteRegister(Module_GetBottomLeftAddress (&modules[1]),offset, data,0, 0)) {
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FILE_LOG(logERROR, ("Could not read bl value. Value read:%d\n", value));
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value = 0;
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}
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}
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return Feb_Control_ReadRegister(offset);
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return 1;
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}
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int Feb_Control_GetInterruptSubframe() {
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// they need to be written separately because the left and right registers have different values for this particular register
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uint32_t offset = DAQ_REG_HRDWRE;
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uint32_t regVal = 0;
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char side[2][10] = {"right", "left"};
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char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
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unsigned int addr[2];
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addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
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addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
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uint32_t value[2] = {0, 0};
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int iloop = 0;
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for(iloop = 0; iloop < 2; ++iloop) {
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if(!Feb_Interface_ReadRegister(addr[iloop], offset, ®Val)) {
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FILE_LOG(logERROR, ("Could not read back %s %s interrupt subframe\n", isTop, side[iloop]));
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return -1;
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}
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value[iloop] = (regVal & DAQ_REG_HRDWRE_INTRRPT_SF_MSK) >> DAQ_REG_HRDWRE_INTRRPT_SF_OFST;
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}
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// inconsistent
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if (value[0] != value[1]) {
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FILE_LOG(logERROR, ("Inconsistent values of interrupt subframe betweeen left %d and right %d\n", value[0], value[1]));
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return -1;
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}
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return value[0];
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}
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int Feb_Control_SetQuad(int val) {
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// no bottom for quad
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if (!Module_TopAddressIsValid(&modules[1])) {
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return 1;
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}
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uint32_t offset = DAQ_REG_HRDWRE;
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FILE_LOG(logINFO, ("Setting Quad to %d in Feb\n", val));
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unsigned int addr = Module_GetTopRightAddress (&modules[1]);
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uint32_t regVal = 0;
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if(!Feb_Interface_ReadRegister(addr, offset, ®Val)) {
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FILE_LOG(logERROR, ("Could not read top right quad reg\n"));
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return 0;
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}
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uint32_t data = ((val == 0) ? (regVal &~ DAQ_REG_HRDWRE_OW_MSK) : ((regVal | DAQ_REG_HRDWRE_OW_MSK) &~ DAQ_REG_HRDWRE_TOP_MSK));
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if(!Feb_Interface_WriteRegister(addr, offset, data, 0, 0)) {
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FILE_LOG(logERROR, ("Could not write 0x%x to top right quad addr 0x%x\n", data, offset));
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return 0;
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}
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return 1;
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}
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uint32_t Feb_Control_ReadRegister(uint32_t offset) {
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uint32_t value=0;
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uint32_t value1=0;
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if (Module_TopAddressIsValid(&modules[1])) {
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if (!Feb_Interface_ReadRegister(Module_GetTopRightAddress (&modules[1]),offset, &value)) {
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FILE_LOG(logERROR, ("Could not read value. Value read:%d\n", value));
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value = 0;
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}
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printf("Read top right addr: 0x%08x\n", value);
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if(!Feb_Interface_ReadRegister(Module_GetTopLeftAddress (&modules[1]),offset, &value1)) {
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FILE_LOG(logERROR, (RED,"Could not read value. Value read:%d\n", value1));
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value1 = 0;
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}
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printf("Read top left addr: 0x%08x\n", value1);
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if (value != value1)
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value = -1;
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} else {
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if (!Feb_Interface_ReadRegister(Module_GetBottomRightAddress (&modules[1]),offset, &value)) {
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FILE_LOG(logERROR, ("Could not read value. Value read:%d\n", value));
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value = 0;
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}
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printf("Read bottom right addr: 0x%08x\n", value);
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if(!Feb_Interface_ReadRegister(Module_GetBottomLeftAddress (&modules[1]),offset, &value1)) {
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FILE_LOG(logERROR, (RED,"Could not read value. Value read:%d\n", value1));
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value1 = 0;
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}
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printf("Read bottom left addr: 0x%08x\n", value1);
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if (value != value1)
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value = -1;
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int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
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uint32_t actualOffset = offset;
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char side[2][10] = {"right", "left"};
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char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
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unsigned int addr[2];
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addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
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addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
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int run[2] = {0, 0};
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// both registers
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if (offset < 0x100) {
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run[0] = 1;
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run[1] = 1;
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}
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// right registers only
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else if (offset >= 0x200) {
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run[0] = 1;
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actualOffset = offset - 0x200;
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}
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// left registers only
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else {
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run[1] = 1;
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actualOffset = offset - 0x100;
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}
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return value;
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int iloop = 0;
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for(iloop = 0; iloop < 2; ++iloop) {
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if(run[iloop]) {
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FILE_LOG(logINFO, ("Writing 0x%x to %s %s 0x%x\n", data, isTop, side[iloop], actualOffset));
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if(!Feb_Interface_WriteRegister(addr[iloop],actualOffset, data, 0, 0)) {
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FILE_LOG(logERROR, ("Could not write 0x%x to %s %s addr 0x%x\n", data, isTop, side[iloop], actualOffset));
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return 0;
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}
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}
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}
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return 1;
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}
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int Feb_Control_ReadRegister(uint32_t offset, uint32_t* retval) {
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uint32_t actualOffset = offset;
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char side[2][10] = {"right", "left"};
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char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
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unsigned int addr[2];
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addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
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addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
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uint32_t value[2] = {0, 0};
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int run[2] = {0, 0};
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// both registers
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if (offset < 0x100) {
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run[0] = 1;
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run[1] = 1;
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}
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// right registers only
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else if (offset >= 0x200) {
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run[0] = 1;
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actualOffset = offset - 0x200;
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}
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// left registers only
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else {
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run[1] = 1;
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actualOffset = offset - 0x100;
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}
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int iloop = 0;
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for(iloop = 0; iloop < 2; ++iloop) {
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if(run[iloop]) {
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if(!Feb_Interface_ReadRegister(addr[iloop],actualOffset, &value[iloop])) {
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FILE_LOG(logERROR, ("Could not read from %s %s addr 0x%x\n", isTop, side[iloop], actualOffset));
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return 0;
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}
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FILE_LOG(logINFO, ("Read 0x%x from %s %s 0x%x\n", value[iloop], isTop, side[iloop], actualOffset));
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*retval = value[iloop];
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// if not the other (left, not right OR right, not left), return the value
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if (!run[iloop ? 0 : 1]) {
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return 1;
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}
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}
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}
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// Inconsistent values
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if (value[0] != value[1]) {
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FILE_LOG(logERROR, ("Inconsistent values read from left 0x%x and right 0x%x\n", value[0], value[1]));
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return 0;
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}
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return 1;
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}
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