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eiger server: quad, interrupt subframe, reg left and right (#45)

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* eiger server: quad, interrupt subframe, reg left and right

*  eiger server: beb can fail in setting up quad, quad and gap pixels
This commit is contained in:
Dhanya Thattil
2019-08-06 10:12:34 +02:00
committed by Erik Fröjdh
parent e17de0609c
commit d72b6c3659
25 changed files with 463 additions and 105 deletions
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11
slsDetectorServers/eigerDetectorServer/Beb.c
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@ -1190,11 +1190,12 @@ void Beb_SetDetectorNumber(uint32_t detid) {
FILE_LOG(logINFO, ("Detector id %d set in UDP Header\n\n", detid));
}
void Beb_SetQuad(int value) {
if (value >= 0) {
Beb_quadEnable = (value == 0 ? 0 : 1);
Beb_SetDetectorPosition(Beb_positions);
}
int Beb_SetQuad(int value) {
if (value < 0)
return OK;
FILE_LOG(logINFO, ("Setting Quad to %d in Beb\n", value));
Beb_quadEnable = (value == 0 ? 0 : 1);
return Beb_SetDetectorPosition(Beb_positions);
}
int Beb_GetQuad() {

2
slsDetectorServers/eigerDetectorServer/Beb.h
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@ -74,7 +74,7 @@ int Beb_Test(unsigned int beb_number);
int Beb_GetBebFPGATemp();
void Beb_SetDetectorNumber(uint32_t detid);
void Beb_SetQuad(int value);
int Beb_SetQuad(int value);
int Beb_GetQuad();
int Beb_SetDetectorPosition(int pos[]);
int Beb_SetStartingFrameNumber(uint64_t value);

208
slsDetectorServers/eigerDetectorServer/FebControl.c
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@ -2014,61 +2014,171 @@ int Feb_Control_SoftwareTrigger() {
return 1;
}
int Feb_Control_SetInterruptSubframe(int val) {
FILE_LOG(logINFO, ("Setting Interrupt Subframe to %d\n", val));
uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
uint32_t value=0;
if (Module_TopAddressIsValid(&modules[1])) {
if (!Feb_Interface_WriteRegister(Module_GetTopRightAddress (&modules[1]),offset, data,0, 0)) {
FILE_LOG(logERROR, ("Could not read tr value. Value read:%d\n", value));
value = 0;
// they need to be written separately because the left and right registers have different values for this particular register
uint32_t offset = DAQ_REG_HRDWRE;
uint32_t regVal = 0;
char side[2][10] = {"right", "left"};
char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
unsigned int addr[2];
addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
int iloop = 0;
for(iloop = 0; iloop < 2; ++iloop) {
// get previous value to keep it
if(!Feb_Interface_ReadRegister(addr[iloop], offset, &regVal)) {
FILE_LOG(logERROR, ("Could not read %s %s interrupt subframe\n", isTop, side[iloop]));
return 0;
}
if(!Feb_Interface_WriteRegister(Module_GetTopLeftAddress (&modules[1]),offset, data,0, 0)) {
FILE_LOG(logERROR, ("Could not read tl value. Value read:%d\n", value));
value = 0;
}
} else {
if (!Feb_Interface_WriteRegister(Module_GetBottomRightAddress (&modules[1]),offset, data,0, 0)) {
FILE_LOG(logERROR, ("Could not read br value. Value read:%d\n", value));
value = 0;
uint32_t data = ((val == 0) ? (regVal &~ DAQ_REG_HRDWRE_INTRRPT_SF_MSK) : (regVal | DAQ_REG_HRDWRE_INTRRPT_SF_MSK));
if(!Feb_Interface_WriteRegister(addr[iloop], offset, data, 0, 0)) {
FILE_LOG(logERROR, ("Could not write 0x%x to %s %s interrupt subframe addr 0x%x\n", data, isTop, side[iloop], offset));
return 0;
}
if(!Feb_Interface_WriteRegister(Module_GetBottomLeftAddress (&modules[1]),offset, data,0, 0)) {
FILE_LOG(logERROR, ("Could not read bl value. Value read:%d\n", value));
value = 0;
}
}
return Feb_Control_ReadRegister(offset);
return 1;
}
int Feb_Control_GetInterruptSubframe() {
// they need to be written separately because the left and right registers have different values for this particular register
uint32_t offset = DAQ_REG_HRDWRE;
uint32_t regVal = 0;
char side[2][10] = {"right", "left"};
char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
unsigned int addr[2];
addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
uint32_t value[2] = {0, 0};
int iloop = 0;
for(iloop = 0; iloop < 2; ++iloop) {
if(!Feb_Interface_ReadRegister(addr[iloop], offset, &regVal)) {
FILE_LOG(logERROR, ("Could not read back %s %s interrupt subframe\n", isTop, side[iloop]));
return -1;
}
value[iloop] = (regVal & DAQ_REG_HRDWRE_INTRRPT_SF_MSK) >> DAQ_REG_HRDWRE_INTRRPT_SF_OFST;
}
// inconsistent
if (value[0] != value[1]) {
FILE_LOG(logERROR, ("Inconsistent values of interrupt subframe betweeen left %d and right %d\n", value[0], value[1]));
return -1;
}
return value[0];
}
int Feb_Control_SetQuad(int val) {
// no bottom for quad
if (!Module_TopAddressIsValid(&modules[1])) {
return 1;
}
uint32_t offset = DAQ_REG_HRDWRE;
FILE_LOG(logINFO, ("Setting Quad to %d in Feb\n", val));
unsigned int addr = Module_GetTopRightAddress (&modules[1]);
uint32_t regVal = 0;
if(!Feb_Interface_ReadRegister(addr, offset, &regVal)) {
FILE_LOG(logERROR, ("Could not read top right quad reg\n"));
return 0;
}
uint32_t data = ((val == 0) ? (regVal &~ DAQ_REG_HRDWRE_OW_MSK) : ((regVal | DAQ_REG_HRDWRE_OW_MSK) &~ DAQ_REG_HRDWRE_TOP_MSK));
if(!Feb_Interface_WriteRegister(addr, offset, data, 0, 0)) {
FILE_LOG(logERROR, ("Could not write 0x%x to top right quad addr 0x%x\n", data, offset));
return 0;
}
return 1;
}
uint32_t Feb_Control_ReadRegister(uint32_t offset) {
uint32_t value=0;
uint32_t value1=0;
if (Module_TopAddressIsValid(&modules[1])) {
if (!Feb_Interface_ReadRegister(Module_GetTopRightAddress (&modules[1]),offset, &value)) {
FILE_LOG(logERROR, ("Could not read value. Value read:%d\n", value));
value = 0;
}
printf("Read top right addr: 0x%08x\n", value);
if(!Feb_Interface_ReadRegister(Module_GetTopLeftAddress (&modules[1]),offset, &value1)) {
FILE_LOG(logERROR, (RED,"Could not read value. Value read:%d\n", value1));
value1 = 0;
}
printf("Read top left addr: 0x%08x\n", value1);
if (value != value1)
value = -1;
} else {
if (!Feb_Interface_ReadRegister(Module_GetBottomRightAddress (&modules[1]),offset, &value)) {
FILE_LOG(logERROR, ("Could not read value. Value read:%d\n", value));
value = 0;
}
printf("Read bottom right addr: 0x%08x\n", value);
if(!Feb_Interface_ReadRegister(Module_GetBottomLeftAddress (&modules[1]),offset, &value1)) {
FILE_LOG(logERROR, (RED,"Could not read value. Value read:%d\n", value1));
value1 = 0;
}
printf("Read bottom left addr: 0x%08x\n", value1);
if (value != value1)
value = -1;
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
uint32_t actualOffset = offset;
char side[2][10] = {"right", "left"};
char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
unsigned int addr[2];
addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
int run[2] = {0, 0};
// both registers
if (offset < 0x100) {
run[0] = 1;
run[1] = 1;
}
// right registers only
else if (offset >= 0x200) {
run[0] = 1;
actualOffset = offset - 0x200;
}
// left registers only
else {
run[1] = 1;
actualOffset = offset - 0x100;
}
return value;
int iloop = 0;
for(iloop = 0; iloop < 2; ++iloop) {
if(run[iloop]) {
FILE_LOG(logINFO, ("Writing 0x%x to %s %s 0x%x\n", data, isTop, side[iloop], actualOffset));
if(!Feb_Interface_WriteRegister(addr[iloop],actualOffset, data, 0, 0)) {
FILE_LOG(logERROR, ("Could not write 0x%x to %s %s addr 0x%x\n", data, isTop, side[iloop], actualOffset));
return 0;
}
}
}
return 1;
}
int Feb_Control_ReadRegister(uint32_t offset, uint32_t* retval) {
uint32_t actualOffset = offset;
char side[2][10] = {"right", "left"};
char isTop[10]; strcpy(isTop, Module_TopAddressIsValid(&modules[1]) ? "top" : "bottom");
unsigned int addr[2];
addr[0] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopRightAddress (&modules[1]) : Module_GetBottomRightAddress (&modules[1]);
addr[1] = Module_TopAddressIsValid(&modules[1]) ? Module_GetTopLeftAddress (&modules[1]) : Module_GetBottomLeftAddress (&modules[1]);
uint32_t value[2] = {0, 0};
int run[2] = {0, 0};
// both registers
if (offset < 0x100) {
run[0] = 1;
run[1] = 1;
}
// right registers only
else if (offset >= 0x200) {
run[0] = 1;
actualOffset = offset - 0x200;
}
// left registers only
else {
run[1] = 1;
actualOffset = offset - 0x100;
}
int iloop = 0;
for(iloop = 0; iloop < 2; ++iloop) {
if(run[iloop]) {
if(!Feb_Interface_ReadRegister(addr[iloop],actualOffset, &value[iloop])) {
FILE_LOG(logERROR, ("Could not read from %s %s addr 0x%x\n", isTop, side[iloop], actualOffset));
return 0;
}
FILE_LOG(logINFO, ("Read 0x%x from %s %s 0x%x\n", value[iloop], isTop, side[iloop], actualOffset));
*retval = value[iloop];
// if not the other (left, not right OR right, not left), return the value
if (!run[iloop ? 0 : 1]) {
return 1;
}
}
}
// Inconsistent values
if (value[0] != value[1]) {
FILE_LOG(logERROR, ("Inconsistent values read from left 0x%x and right 0x%x\n", value[0], value[1]));
return 0;
}
return 1;
}

8
slsDetectorServers/eigerDetectorServer/FebControl.h
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@ -151,7 +151,11 @@ int64_t Feb_Control_GetMeasuredPeriod();
int64_t Feb_Control_GetSubMeasuredPeriod();
int Feb_Control_SoftwareTrigger();
int Feb_Control_SetInterruptSubframe(int val);
int Feb_Control_GetInterruptSubframe();
int Feb_Control_SetQuad(int val);
uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
uint32_t Feb_Control_ReadRegister(uint32_t offset);
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
int Feb_Control_ReadRegister(uint32_t offset, uint32_t* retval);

10
slsDetectorServers/eigerDetectorServer/FebRegisterDefs.h
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@ -14,8 +14,16 @@
#define DAQ_REG_SUBFRAME_EXPOSURES 6
#define DAQ_REG_SUBFRAME_PERIOD 7 //also pg and fifo status register
#define DAQ_REG_HRDWRE 12
#define DAQ_REG_RO_OFFSET 12
#define DAQ_REG_HRDWRE_OW_OFST (0)
#define DAQ_REG_HRDWRE_OW_MSK (0x00000001 << DAQ_REG_HRDWRE_OW_OFST)
#define DAQ_REG_HRDWRE_TOP_OFST (1)
#define DAQ_REG_HRDWRE_TOP_MSK (0x00000001 << DAQ_REG_HRDWRE_TOP_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_OFST (3)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK (0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_RO_OFFSET 20
#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
#define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)

BIN
slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_developer
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Binary file not shown.

50
slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c
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@ -464,19 +464,25 @@ void setupDetector() {
/* advanced read/write reg */
uint32_t writeRegister(uint32_t offset, uint32_t data) {
int writeRegister(uint32_t offset, uint32_t data) {
#ifdef VIRTUAL
return 0;
return OK;
#else
return Feb_Control_WriteRegister(offset, data);
if(!Feb_Control_WriteRegister(offset, data)) {
return FAIL;
}
return OK;
#endif
}
uint32_t readRegister(uint32_t offset) {
int readRegister(uint32_t offset, uint32_t* retval) {
#ifdef VIRTUAL
return 0;
return OK;
#else
return Feb_Control_ReadRegister(offset);
if(!Feb_Control_ReadRegister(offset, retval)) {
return FAIL;
}
return OK;
#endif
}
@ -1310,10 +1316,19 @@ int setDetectorPosition(int pos[]) {
#endif
}
void setQuad(int value) {
int setQuad(int value) {
if (value < 0) {
return OK;
}
#ifndef VIRTUAL
Beb_SetQuad(value);
if (Beb_SetQuad(value) == FAIL) {
return FAIL;
}
if (!Feb_Control_SetQuad(value)) {
return FAIL;
}
#endif
return OK;
}
int getQuad() {
@ -1324,6 +1339,25 @@ int getQuad() {
#endif
}
int setInterruptSubframe(int value) {
if(value < 0)
return FAIL;
#ifndef VIRTUAL
if(!Feb_Control_SetInterruptSubframe(value)) {
return FAIL;
}
return OK;
#endif
}
int getInterruptSubframe() {
#ifdef VIRTUAL
return 0;
#else
return Feb_Control_GetInterruptSubframe();
#endif
}
int enableTenGigabitEthernet(int val) {
if (val!=-1) {
FILE_LOG(logINFO, ("Setting 10Gbe: %d\n", (val > 0) ? 1 : 0));

2
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
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@ -1,7 +1,7 @@
#pragma once
#include "sls_detector_defs.h"
#define REQUIRED_FIRMWARE_VERSION (22)
#define REQUIRED_FIRMWARE_VERSION (24)
#define IDFILECOMMAND "more /home/root/executables/detid.txt"
#define STATUS_IDLE 0