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external signals

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This commit is contained in:
maliakal_d
2020-05-20 17:05:42 +02:00
parent 9475e01062
commit d71e40729a
18 changed files with 370 additions and 113 deletions
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63
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -21,7 +21,7 @@
/* ASIC Digital Interface. Data recovery core */
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/xxx/adif/adif_ctrl.vhd
/* Formatting of data core */
#define BASE_FMT (0x0120) // 0x1806_0120 - 0x1806_012F
@ -30,12 +30,16 @@
#define BASE_PKT (0x0130) // 0x1806_0130 - 0x1806_013F
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/pkt/pkt_ctrl.vhd
/** Pipeline (Timing Rec) */
#define BASE_PIPELINE (0x0140) // 0x1806_0140 - 0x1806_014F
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/xxx/MythenIIITriggerBoard/timingReceier.vhd
/* ASIC Exposure Control */
#define BASE_ASIC_EXP (0x0180) // 0x1806_0180 - 0x1806_01BF
/* Pattern control and status */
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/xxx/pattern_flow/pattern_flow_ctrl.vhd
/* Flow control and status */
#define BASE_FLOW_CONTROL (0x00400) // 0x1806_0400 - 0x1806_04FF
@ -161,6 +165,61 @@
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Pipeline -------------------------------------------------------------*/
/** DINF1 Master Input Register */
#define DINF1_REG (0x00 * REG_OFFSET + BASE_PIPELINE)
#define DINF1_TRIGGER_BYPASS_OFST (0)
#define DINF1_TRIGGER_BYPASS_MSK (0x00000001 << DINF1_TRIGGER_BYPASS_OFST)
#define DINF1_BYPASS_GATE_OFST (1)
#define DINF1_BYPASS_GATE_MSK (0x00000007 << DINF1_BYPASS_GATE_OFST)
#define DINF1_INVERSION_OFST (4)
#define DINF1_INVERSION_MSK (0x0000000F << DINF1_INVERSION_OFST)
#define DINF1_RISING_TRIGGER_OFST (8)
#define DINF1_RISING_TRIGGER_MSK (0x00000001 << DINF1_RISING_TRIGGER_OFST)
#define DINF1_RISING_GATE_OFST (9)
#define DINF1_RISING_GATE_MSK (0x00000007 << DINF1_RISING_GATE_OFST)
#define DINF1_FALLING_OFST (12)
#define DINF1_FALLING_MSK (0x0000000F << DINF1_FALLING_OFST)
/** DOUTIF1 Master Ouput Register */
#define DOUTIF1_REG (0x01 * REG_OFFSET + BASE_PIPELINE)
#define DOUTIF1_BYPASS_OFST (0)
#define DOUTIF1_BYPASS_MSK (0x0000000F << DOUTIF1_BYPASS_OFST)
#define DOUTIF1_INVERSION_OFST (4)
#define DOUTIF1_INVERSION_MSK (0x0000000F << DOUTIF1_INVERSION_OFST)
#define DOUTIF1_RISING_OFST (8)
#define DOUTIF1_RISING_MSK (0x0000000F << DOUTIF1_RISING_OFST)
#define DOUTIF1_FALLING_OFST (12)
#define DOUTIF1_FALLING_MSK (0x0000000F << DOUTIF1_FALLING_OFST)
/** DINF2 Slave Input Register */
#define DINF2_REG (0x02 * REG_OFFSET + BASE_PIPELINE)
#define DINF2_BYPASS_OFST (0)
#define DINF2_BYPASS_MSK (0x0000000F << DINF2_BYPASS_OFST)
#define DINF2_INVERSION_OFST (4)
#define DINF2_INVERSION_MSK (0x0000000F << DINF2_INVERSION_OFST)
#define DINF2_RISING_OFST (8)
#define DINF2_RISING_MSK (0x0000000F << DINF2_RISING_OFST)
#define DINF2_FALLING_OFST (12)
#define DINF2_FALLING_MSK (0x0000000F << DINF2_FALLING_OFST)
/* Pulse length after rising edge TODO (maybe fix a value for port 1 later )*/
#define DOUTIF_RISING_LNGTH_REG (0x03 * REG_OFFSET + BASE_PIPELINE)
#define DOUTIF_RISING_LNGTH_PORT_1_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_1_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_1_OFST)
#define DOUTIF_RISING_LNGTH_PORT_2_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_2_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_2_OFST)
#define DOUTIF_RISING_LNGTH_PORT_3_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_3_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_3_OFST)
#define DOUTIF_RISING_LNGTH_PORT_4_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_4_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_4_OFST)
/* ASIC Exposure Control registers
* --------------------------------------------------*/

96
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

@ -434,6 +434,7 @@ void setupDetector() {
setExpTime(i, DEFAULT_GATE_WIDTH);
setGateDelay(i, DEFAULT_GATE_DELAY);
}
setInitialExtSignals();
}
int setDefaultDacs() {
@ -1241,6 +1242,101 @@ enum timingMode getTiming() {
}
}
void setInitialExtSignals() {
LOG(logINFOBLUE, ("Setting Initial External Signals\n"));
// default, everything is 0
// bypass everything
// (except master input can edge detect)
bus_w(DINF1_REG, DINF1_BYPASS_GATE_MSK);
bus_w(DOUTIF1_REG, DOUTIF1_BYPASS_MSK);
bus_w(DINF2_REG, DINF2_BYPASS_MSK);
// master input can edge detect, so rising is 1
bus_w(DINF1_REG, bus_r(DINF1_REG) | DINF1_RISING_TRIGGER_MSK);
}
void setExtSignal(int signalIndex, enum externalSignalFlag mode) {
LOG(logDEBUG1, ("Setting signal flag[%d] to %d\n", signalIndex, mode));
if (signalIndex == 0 && mode != TRIGGER_IN_RISING_EDGE &&
mode != TRIGGER_IN_FALLING_EDGE) {
return;
}
// getting addr and mask for each signal
uint32_t addr = 0;
uint32_t mask = 0;
if (signalIndex <= 3) {
addr = DINF1_REG;
int offset = DINF1_INVERSION_OFST + signalIndex;
mask = (1 << offset);
} else {
addr = DOUTIF1_REG;
int offset = DOUTIF1_INVERSION_OFST + signalIndex - 4;
mask = (1 << offset);
}
LOG(logINFO, ("addr: 0x%x mask:0x%x\n", addr, mask));
switch (mode) {
case TRIGGER_IN_RISING_EDGE:
LOG(logINFO, ("Setting External Master Input Signal flag: Trigger in "
"Rising Edge\n"));
bus_w(addr, bus_r(addr) & ~mask);
break;
case TRIGGER_IN_FALLING_EDGE:
LOG(logINFO, ("Setting External Master Input Signal flag: Trigger in "
"Falling Edge\n"));
bus_w(addr, bus_r(addr) | mask);
break;
case INVERSION_ON:
LOG(logINFO, ("Setting External Master %s Signal flag: Inversion on\n",
(signalIndex <= 3 ? "Input" : "Output")));
bus_w(addr, bus_r(addr) | mask);
break;
case INVERSION_OFF:
LOG(logINFO, ("Setting External Master %s Signal flag: Inversion offn",
(signalIndex <= 3 ? "Input" : "Output")));
bus_w(addr, bus_r(addr) & ~mask);
break;
default:
LOG(logERROR,
("Extsig (signal mode) %d not defined for this detector\n", mode));
return;
}
}
int getExtSignal(int signalIndex) {
// getting addr and mask for each signal
uint32_t addr = 0;
uint32_t mask = 0;
if (signalIndex <= 3) {
addr = DINF1_REG;
int offset = DINF1_INVERSION_OFST + signalIndex;
mask = (1 << offset);
} else {
addr = DOUTIF1_REG;
int offset = DOUTIF1_INVERSION_OFST + signalIndex - 4;
mask = (1 << offset);
}
LOG(logINFO, ("addr: 0x%x mask:0x%x\n", addr, mask));
int val = bus_r(addr) & mask;
// master input trigger signal
if (signalIndex == 0) {
if (val) {
return TRIGGER_IN_FALLING_EDGE;
} else {
return TRIGGER_IN_RISING_EDGE;
}
} else {
if (val) {
return INVERSION_ON;
} else {
return INVERSION_OFF;
}
}
}
int configureMAC() {
uint32_t srcip = udpDetails.srcip;

1
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -21,6 +21,7 @@
#define TYPE_MYTHEN3_MODULE_VAL (93)
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
#define MAX_EXT_SIGNALS (8)
/** Default Parameters */
#define DEFAULT_INTERNAL_GATES (1)