detectors/slsDetectorPackage
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storagecells for jungfrauvchip1.1: cannot set addl, storagecelldealy and storagecell start is only from 0-3

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This commit is contained in:
maliakal_d
2021-07-30 15:32:36 +02:00
parent 6467b04c37
commit d64df39301
7 changed files with 63 additions and 24 deletions
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35
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
View File

@ -458,8 +458,13 @@ void setupDetector() {
setPeriod(DEFAULT_PERIOD);
setDelayAfterTrigger(DEFAULT_DELAY);
setNumAdditionalStorageCells(DEFAULT_NUM_STRG_CLLS);
setStorageCellDelay(DEFAULT_STRG_CLL_DLY);
selectStoragecellStart(DEFAULT_STRG_CLL_STRT);
if (getChipVersion() == 11) {
selectStoragecellStart(DEFAULT_STRG_CLL_STRT_CHIP11);
} else {
selectStoragecellStart(DEFAULT_STRG_CLL_STRT);
// not applicable for chipv1.1
setStorageCellDelay(DEFAULT_STRG_CLL_DLY);
}
/*setClockDivider(RUN_CLK, HALF_SPEED); depends if all the previous stuff
* works*/
setTiming(DEFAULT_TIMING_MODE);
@ -773,14 +778,30 @@ uint32_t getADCInvertRegister() {
/* parameters - timer */
int selectStoragecellStart(int pos) {
int value = pos;
uint32_t addr = DAQ_REG;
uint32_t mask = DAQ_STRG_CELL_SLCT_MSK;
int offset = DAQ_STRG_CELL_SLCT_OFST;
if (getChipVersion() == 11) {
value = 1 << pos;
addr = CONFIG_V11_REG;
mask = CONFIG_V11_STRG_CLL_MSK;
offset = CONFIG_V11_STRG_CLL_OFST;
}
if (pos >= 0) {
LOG(logINFO, ("Setting storage cell start: %d\n", pos));
bus_w(DAQ_REG, bus_r(DAQ_REG) & ~DAQ_STRG_CELL_SLCT_MSK);
bus_w(DAQ_REG, bus_r(DAQ_REG) | ((pos << DAQ_STRG_CELL_SLCT_OFST) &
DAQ_STRG_CELL_SLCT_MSK));
bus_w(addr, bus_r(addr) & ~mask);
bus_w(addr, bus_r(addr) | ((value << offset) & mask));
}
return ((bus_r(addr) & mask) >> offset);
}
int getMaxStoragecellStart() {
if (getChipVersion() == 11) {
return MAX_STORAGE_CELL_CHIP11_VAL;
} else {
return MAX_STORAGE_CELL_VAL;
}
return ((bus_r(DAQ_REG) & DAQ_STRG_CELL_SLCT_MSK) >>
DAQ_STRG_CELL_SLCT_OFST);
}
int setNextFrameNumber(uint64_t value) {

2
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
View File

@ -102,6 +102,7 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define DEFAULT_TMP_THRSHLD (65 * 1000) // milli degree Celsius
#define DEFAULT_NUM_STRG_CLLS (0)
#define DEFAULT_STRG_CLL_STRT (0xf)
#define DEFAULT_STRG_CLL_STRT_CHIP11 (0x3)
#define DEFAULT_STRG_CLL_DLY (0)
#define HIGHVOLTAGE_MIN (60)
@ -113,6 +114,7 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
#define MAX_STORAGE_CELL_VAL (15) // 0xF
#define MAX_STORAGE_CELL_CHIP11_VAL (3)
#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
#define ACQ_TIME_MIN_CLOCK (2)