mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-27 16:50:02 +02:00
Changes to jctb server to correctly change the power supplies
This commit is contained in:
parent
511d3e3970
commit
d5f80831dd
61
slsDetectorSoftware/jctbDetectorServer/Makefile.ctb
Normal file
61
slsDetectorSoftware/jctbDetectorServer/Makefile.ctb
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# $Id: Makefile,v 1.1.1.1 2006/02/04 03:35:01 freza Exp $
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# first compile
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# make cris-axis-linux-gnu
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CROSS = bfin-uclinux-
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CC = $(CROSS)gcc
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CFLAGS += -Wall -DMOENCHD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 -DCTB #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
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PROGS= jungfrauDetectorServerTest
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INSTDIR= /tftpboot
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INSTMODE= 0777
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BINS = testlib_sharedlibc
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SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c mcb_funcs.c sharedmemory.c
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OBJS = $(SRCS:%.c=%.o)
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all: clean $(PROGS)
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test: clean jungfrauADCTEst
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boot: $(OBJS)
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jungfrauDetectorServerTest: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
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jungfrauDetectorServer: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
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jungfrauADCTEst: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DTESTADC
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install: $(PROGS)
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$(INSTALL) -d $(INSTDIR)
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$(INSTALL) -m $(INSTMODE) $(PROGS) $(INSTDIR)
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romfs:
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$(ROMFSINST) /bin/$(PROGS)
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clean:
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rm -rf $(PROGS) *.o *.gdb
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1
slsDetectorSoftware/jctbDetectorServer/ansi.h
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1
slsDetectorSoftware/jctbDetectorServer/ansi.h
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../../slsReceiverSoftware/include/ansi.h
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1
slsDetectorSoftware/jctbDetectorServer/communication_funcs.c
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1
slsDetectorSoftware/jctbDetectorServer/communication_funcs.c
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../commonFiles/communication_funcs.c
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1
slsDetectorSoftware/jctbDetectorServer/communication_funcs.h
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1
slsDetectorSoftware/jctbDetectorServer/communication_funcs.h
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../commonFiles/communication_funcs.h
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3664
slsDetectorSoftware/jctbDetectorServer/firmware_funcs.c
Executable file
3664
slsDetectorSoftware/jctbDetectorServer/firmware_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
214
slsDetectorSoftware/jctbDetectorServer/firmware_funcs.h
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214
slsDetectorSoftware/jctbDetectorServer/firmware_funcs.h
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#ifndef FIRMWARE_FUNCS_H
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#define FIRMWARE_FUNCS_H
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#include "sls_detector_defs.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <fcntl.h>
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#include <stdarg.h>
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#include <unistd.h>
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//#include <asm/page.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <stdarg.h>
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#include <unistd.h>
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int mapCSP0(void);
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u_int16_t bus_r16(u_int32_t offset);
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u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
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u_int32_t bus_w(u_int32_t offset, u_int32_t data);
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u_int32_t bus_r(u_int32_t offset);
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int setPhaseShiftOnce();
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int phaseStep(int st);
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int getPhase();
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int cleanFifo();
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int setDAQRegister();
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u_int32_t putout(char *s, int modnum);
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u_int32_t readin(int modnum);
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u_int32_t setClockDivider(int d, int ic);
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u_int32_t getClockDivider(int ic);
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void resetPLL();
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u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
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u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
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u_int32_t setSetLength(int d);
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u_int32_t getSetLength();
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u_int32_t setWaitStates(int d);
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u_int32_t getWaitStates();
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u_int32_t setTotClockDivider(int d);
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u_int32_t getTotClockDivider();
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u_int32_t setTotDutyCycle(int d);
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u_int32_t getTotDutyCycle();
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u_int32_t setOversampling(int d);
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u_int32_t adcPipeline(int d);
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u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
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int getExtSignal(int d);
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u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
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int getFPGASignal(int d);
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int setTiming(int t);
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int setConfigurationRegister(int d);
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int setToT(int d);
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int setContinousReadOut(int d);
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int startReceiver(int d);
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int setDACRegister(int idac, int val, int imod);
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int getDacRegister(int dacnum);
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int getTemperature(int tempSensor,int imod);
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int initHighVoltage(int val,int imod);
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int initConfGain(int isettings,int val,int imod);
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int setADC(int adc);
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//int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
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int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int detipad,int ival,uint32_t destport);
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int getAdcConfigured();
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u_int64_t getDetectorNumber();
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u_int32_t getFirmwareVersion();
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u_int32_t getFirmwareSVNVersion();
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int testFifos(void);
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u_int32_t testFpga(void);
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u_int32_t testRAM(void);
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int testBus(void);
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int setDigitalTestBit(int ival);
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int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
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int64_t get64BitReg(int aLSB, int aMSB);
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int64_t setFrames(int64_t value);
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int64_t getFrames();
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int64_t setExposureTime(int64_t value);
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int64_t getExposureTime();
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int64_t setGates(int64_t value);
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int64_t getGates();
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int64_t setDelay(int64_t value);
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int64_t getDelay();
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int64_t setPeriod(int64_t value);
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int64_t getPeriod();
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int64_t setTrains(int64_t value);
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int64_t getTrains();
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int64_t setProbes(int64_t value);
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int64_t getProbes();
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int64_t getProgress();
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int64_t setProgress();
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int64_t getActualTime();
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int64_t getMeasurementTime();
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int64_t getFramesFromStart();
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u_int32_t runBusy(void);
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u_int32_t runState(void);
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u_int32_t dataPresent(void);
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int startStateMachine();
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int stopStateMachine();
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int startReadOut();
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u_int32_t fifoReset(void);
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u_int32_t fifoReadCounter(int fifonum);
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u_int32_t fifoReadStatus();
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u_int32_t fifo_full(void);
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u_int16_t* fifo_read_event(int ns);
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u_int16_t* fifo_read_frame();
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u_int32_t* decode_data(int* datain);
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//u_int32_t move_data(u_int64_t* datain, u_int64_t* dataout);
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int setDynamicRange(int dr);
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int getDynamicRange();
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int getNModBoard();
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int setNMod(int n);
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int getNMod();
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int setStoreInRAM(int b);
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int allocateRAM();
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int writeADC(int addr, int val);
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int prepareADC();
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int clearRAM();
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int setMaster(int f);
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int setSynchronization(int s);
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int loadImage(int index, short int ImageVals[]);
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int readCounterBlock(int startACQ, short int CounterVals[]);
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int resetCounterBlock(int startACQ);
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int calibratePedestal(int frames);
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uint64_t writePatternWord(int addr, uint64_t word);
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uint64_t writePatternIOControl(uint64_t word);
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uint64_t writePatternClkControl(uint64_t word);
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int setPatternLoop(int level, int *start, int *stop, int *n);
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int setPatternWaitAddress(int level, int addr);
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uint64_t setPatternWaitTime(int level, uint64_t t);
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void initDac(int dacnum);
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int setDac(int dacnum,int dacvalue);
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int setPower(int ind, int val);
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ROI *setROI(int nroi,ROI* arg,int *retvalsize, int *ret);
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int getChannels();
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/*
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u_int32_t setNBits(u_int32_t);
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u_int32_t getNBits();
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*/
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/*
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//move to mcb_funcs?
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int readOutChan(int *val);
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u_int32_t getModuleNumber(int modnum);
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int testShiftIn(int imod);
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int testShiftOut(int imod);
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int testShiftStSel(int imod);
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int testDataInOut(int num, int imod);
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int testExtPulse(int imod);
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int testExtPulseMux(int imod, int ow);
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int testDataInOutMux(int imod, int ow, int num);
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int testOutMux(int imod);
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int testFpgaMux(int imod);
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int calibration_sensor(int num, int *values, int *dacs) ;
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int calibration_chip(int num, int *values, int *dacs);
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*/
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#endif
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11
slsDetectorSoftware/jctbDetectorServer/gitInfoMoench.h
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11
slsDetectorSoftware/jctbDetectorServer/gitInfoMoench.h
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//#define SVNPATH ""
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#define SVNURL "git@gitorious.psi.ch:sls_det_software/sls_detector_software.git/moenchDetectorServer"
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//#define SVNREPPATH ""
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#define SVNREPUUID "046a469b1e6582c4c55bd6eaeb4818b618d0a9a9"
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//#define SVNREV 0x14
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//#define SVNKIND ""
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//#define SVNSCHED ""
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#define SVNAUTH "Maliakal_Dhanya"
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#define SVNREV 0x14
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#define SVNDATE 0x20140603
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//
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11
slsDetectorSoftware/jctbDetectorServer/gitInfoMoenchTmp.h
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11
slsDetectorSoftware/jctbDetectorServer/gitInfoMoenchTmp.h
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//#define SVNPATH ""
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#define SVNURL ""
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//#define SVNREPPATH ""
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#define SVNREPUUID ""
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//#define SVNREV ""
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//#define SVNKIND ""
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//#define SVNSCHED ""
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#define SVNAUTH ""
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#define SVNREV ""
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#define SVNDATE ""
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//
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BIN
slsDetectorSoftware/jctbDetectorServer/jungfrauDetectorServerTest
Executable file
BIN
slsDetectorSoftware/jctbDetectorServer/jungfrauDetectorServerTest
Executable file
Binary file not shown.
2701
slsDetectorSoftware/jctbDetectorServer/mcb_funcs.c
Executable file
2701
slsDetectorSoftware/jctbDetectorServer/mcb_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
174
slsDetectorSoftware/jctbDetectorServer/mcb_funcs.h
Executable file
174
slsDetectorSoftware/jctbDetectorServer/mcb_funcs.h
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#ifdef MCB_FUNCS
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#ifndef MCB_FUNCS_H
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#define MCB_FUNCS_H
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#include "sls_detector_defs.h"
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#define RGPRVALS {100,50,200}
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#define RGSH1VALS {300,200,400}
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#define RGSH2VALS {260,300,260}
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#define DEFAULTGAIN {11.66,9.32,14.99}
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#define DEFAULTOFFSET {817.5,828.6,804.2}
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// DAC definitions
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enum dacsVal{VDAC0, VDAC1, VDAC2, VDAC3, VDAC4, VDAC5, VDAC6, VDAC7, HIGH_VOLTAGE, CONFGAIN};
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/* DAC adresses */
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#define DACCS {0,0,1,1,2,2,3,3,4,4,5,5,6,6}
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#define DACADDR {0,1,0,1,0,1,0,1,0,1,0,1,0,1}
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//Register Definitions for temp,hv,dac gain
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enum adcVals{TEMP_FPGA, TEMP_ADC};
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//dynamic range
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/*
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#define MAX5523 commented out by dhanya
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#ifndef MAX5523
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#define MAX5533
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#endif
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#ifdef MAX5533
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#define DAC_DR 4096
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#endif
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#ifdef MAX5523
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*/
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#define DAC_DR 1024
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//#endif
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//reference voltage
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#define DAC_REFOUT1
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#ifdef DAC_REFOUT2
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#define DAC_MAX 2.425
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#define DAC_REFOUT 2
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#define DAC_REFOUT1
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#endif
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#ifdef DAC_REFOUT3
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#define DAC_MAX 3.885
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#define DAC_REFOUT 3
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#define DAC_REFOUT1
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#endif
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#ifdef DAC_REFOUT0
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#define DAC_MAX 1.214
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#define DAC_REFOUT 0
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#endif
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#ifdef DAC_REFOUT1
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#define DAC_MAX 1.940
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#define DAC_REFOUT 1
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#endif
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/* dac calibration constants */
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#define VA 1.11
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#define CVTRIM 52.430851
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#define BVTRIM -0.102022
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#define AVTRIM 0.000050
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#define PARTREF {100,1.55,-2.5,-2.5,0,-2.5}
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#define PARTR1 {78,10,10,10,10,10}
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#define PARTR2 {0,4.7,27,47,22,47}
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//chip shiftin register meaning
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#define OUTMUX_OFFSET 20
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#define PROBES_OFFSET 4
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#define OUTBUF_OFFSET 0
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void showbits(int h);
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int initDetector();
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int copyChannel(sls_detector_channel *destChan, sls_detector_channel *srcChan);
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int copyChip(sls_detector_chip *destChip, sls_detector_chip *srcChip);
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int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
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/* Register commands */
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/* int clearDACSregister(int imod ); */
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/* int nextDAC(int imod ); */
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int clearCSregister(int imod );
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int setCSregister(int imod );
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int nextChip(int imod );
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int firstChip(int imod );
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int clearSSregister(int imod );
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int setSSregister(int imod );
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int nextStrip(int imod );
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int selChannel(int strip,int imod );
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int selChip(int chip,int imod );
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int selMod(int mod,int imod );
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/* DACs routines */
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/* int program_one_dac(int addr, int value,int imod ); */
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/* int set_one_dac(int imod); */
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/* int initDAC(int dac_addr, int value,int imod ); */
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/* int initDACs(int* v,int imod ); */
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/* int initDACbyIndex(int ind,int val, int imod); */
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/* int initDACbyIndexDACU(int ind,int val, int imod); */
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/* int getDACbyIndexDACU(int ind, int imod); */
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/* int getThresholdEnergy(); */
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/* int setThresholdEnergy(int ethr); */
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int setSettings(int i,int imod);
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/* Other DAC index routines*/
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int getTemperatureByModule(int tempSensor, int imod);
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int initHighVoltageByModule(int val, int imod);
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int initConfGainByModule(int isettings,int val,int imod);
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/* Initialization*/
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int initChannel(int ft,int cae, int ae, int coe, int ocoe, int counts,int imod );
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int initChannelbyNumber(sls_detector_channel myChan);
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int getChannelbyNumber(sls_detector_channel*);
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int getTrimbit(int imod, int ichip, int ichan);
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int initChip(int obe, int ow,int imod );
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int initChipWithProbes(int obe, int ow,int nprobes, int imod);
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//int getNProbes();
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|
||||
int initChipbyNumber(sls_detector_chip myChip);
|
||||
int getChipbyNumber(sls_detector_chip*);
|
||||
int initMCBregisters(int cm,int imod );
|
||||
int initModulebyNumber(sls_detector_module);
|
||||
int getModulebyNumber(sls_detector_module*);
|
||||
|
||||
/* To chips */
|
||||
int clearCounter(int imod );
|
||||
int clearOutReg(int imod);
|
||||
int setOutReg(int imod );
|
||||
int extPulse(int ncal,int imod );
|
||||
int calPulse(int ncal,int imod );
|
||||
int counterClear(int imod );
|
||||
int countEnable(int imod );
|
||||
int counterSet(int imod );
|
||||
|
||||
|
||||
/* moved from firmware_funcs */
|
||||
|
||||
int readOutChan(int *val);
|
||||
|
||||
int getModuleNumber(int modnum);
|
||||
int testShiftIn(int imod);
|
||||
int testShiftOut(int imod);
|
||||
int testShiftStSel(int imod);
|
||||
int testDataInOut(int num, int imod);
|
||||
int testExtPulse(int imod);
|
||||
int testExtPulseMux(int imod, int ow);
|
||||
int testDataInOutMux(int imod, int ow, int num);
|
||||
int testOutMux(int imod);
|
||||
int testFpgaMux(int imod);
|
||||
int calibration_sensor(int num, int *values, int *dacs) ;
|
||||
int calibration_chip(int num, int *values, int *dacs);
|
||||
|
||||
|
||||
|
||||
//ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
529
slsDetectorSoftware/jctbDetectorServer/registers_m.h
Executable file
529
slsDetectorSoftware/jctbDetectorServer/registers_m.h
Executable file
@ -0,0 +1,529 @@
|
||||
#ifndef REGISTERS_G_H
|
||||
#define REGISTERS_G_H
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
/* Definitions for FPGA*/
|
||||
#define CSP0 0x20200000
|
||||
#define MEM_SIZE 0x100000
|
||||
|
||||
|
||||
|
||||
/* values defined for FPGA */
|
||||
#define MCSNUM 0x0
|
||||
#define FIXED_PATT_VAL 0xacdc1980
|
||||
|
||||
|
||||
#define FPGA_INIT_PAT 0x60008
|
||||
#define FPGA_INIT_ADDR 0xb0000000
|
||||
|
||||
//#ifdef JUNGFRAU_DHANYA
|
||||
#define POWER_ON_REG 0x5e<<11
|
||||
#define ADCREG1 0x08
|
||||
#define ADCREG2 0x14//20
|
||||
#define ADCREG3 0x4
|
||||
#define ADCREG4 0x5
|
||||
#define ADCREG_VREFS 24
|
||||
#define DBIT_PIPELINE_REG 89<<11 //0x59 same PATTERN_N_LOOP2_REG
|
||||
#define MEM_MACHINE_FIFOS_REG 79<<11 //from gotthard
|
||||
#define CONFGAIN_REG 93<<11 //from gotthard
|
||||
#define ADC_PIPELINE_REG 66<<11 //0x42 same as ADC_OFFSET_REG
|
||||
//#endif
|
||||
|
||||
#define ADC_OFFSET_REG 93<<11 //same as DAQ_REG
|
||||
#define ADC_INVERSION_REG 67<<11
|
||||
|
||||
#define DAC_REG 64<<11//0x17<<11// control the dacs
|
||||
//ADC
|
||||
#define ADC_WRITE_REG 65<<11//0x18<<11
|
||||
//#define ADC_SYNC_REG 66<<11//0x19<<11
|
||||
//#define HV_REG 67<<11//0x20<<11
|
||||
|
||||
|
||||
|
||||
|
||||
//#define MUTIME_REG 0x1a<<11
|
||||
//temperature
|
||||
#define TEMP_IN_REG 0x1b<<11
|
||||
#define TEMP_OUT_REG 0x1c<<11
|
||||
//configure MAC
|
||||
#define TSE_CONF_REG 0x1d<<11
|
||||
#define ENET_CONF_REG 0x1e<<11
|
||||
//#define WRTSE_SHAD_REG 0x1f<<11
|
||||
//HV
|
||||
|
||||
|
||||
#define DUMMY_REG 68<<11//0x21<<11
|
||||
#define FPGA_VERSION_REG 0<<11 //0x22<<11
|
||||
#define PCB_REV_REG 0<<11
|
||||
#define FIX_PATT_REG 1<<11 //0x23<<11
|
||||
#define CONTROL_REG 79<<11//0x24<<11
|
||||
#define STATUS_REG 2<<11 //0x25<<11
|
||||
#define CONFIG_REG 77<<11//0x26<<11
|
||||
#define EXT_SIGNAL_REG 78<<11// 0x27<<11
|
||||
#define FPGA_SVN_REG 0x29<<11
|
||||
|
||||
|
||||
#define CHIP_OF_INTRST_REG 0x2A<<11
|
||||
|
||||
//FIFO
|
||||
#define LOOK_AT_ME_REG 3<<11 //0x28<<11
|
||||
#define SYSTEM_STATUS_REG 4<<11
|
||||
|
||||
#define FIFO_DATA_REG 6<<11
|
||||
#define FIFO_STATUS_REG 7<<11
|
||||
|
||||
|
||||
#define FIFO_DATA_REG_OFF 0x50<<11 ///////
|
||||
//to read back dac registers
|
||||
//#define MOD_DACS1_REG 0x65<<11
|
||||
//#define MOD_DACS2_REG 0x66<<11
|
||||
//#define MOD_DACS3_REG 0x67<<11
|
||||
|
||||
//user entered
|
||||
|
||||
|
||||
#define NSAMPLES_REG 95<<11
|
||||
|
||||
|
||||
|
||||
|
||||
#define GET_ACTUAL_TIME_LSB_REG 16<<11
|
||||
#define GET_ACTUAL_TIME_MSB_REG 17<<11
|
||||
|
||||
#define GET_MEASUREMENT_TIME_LSB_REG 38<<11
|
||||
#define GET_MEASUREMENT_TIME_MSB_REG 38<<11
|
||||
|
||||
|
||||
#define SET_DELAY_LSB_REG 96<<11 //0x68<<11
|
||||
#define SET_DELAY_MSB_REG 97<<11 //0x69<<11
|
||||
#define GET_DELAY_LSB_REG 18<<11//0x6a<<11
|
||||
#define GET_DELAY_MSB_REG 19<<11//0x6b<<11
|
||||
|
||||
#define SET_CYCLES_LSB_REG 98<<11//0x6c<<11
|
||||
#define SET_CYCLES_MSB_REG 99<<11//0x6d<<11
|
||||
#define GET_CYCLES_LSB_REG 20<<11//0x6e<<11
|
||||
#define GET_CYCLES_MSB_REG 21<<11//0x6f<<11
|
||||
|
||||
#define SET_FRAMES_LSB_REG 100<<11//0x70<<11
|
||||
#define SET_FRAMES_MSB_REG 101<<11//0x71<<11
|
||||
#define GET_FRAMES_LSB_REG 22<<11//0x72<<11
|
||||
#define GET_FRAMES_MSB_REG 23<<11//0x73<<11
|
||||
|
||||
#define SET_PERIOD_LSB_REG 102<<11//0x74<<11
|
||||
#define SET_PERIOD_MSB_REG 103<<11//0x75<<11
|
||||
#define GET_PERIOD_LSB_REG 24<<11//0x76<<11
|
||||
#define GET_PERIOD_MSB_REG 25<<11//0x77<<11
|
||||
|
||||
#define SET_EXPTIME_LSB_REG 104<<11//0x78<<11
|
||||
#define SET_EXPTIME_MSB_REG 105<<11//0x79<<11
|
||||
#define GET_EXPTIME_LSB_REG 26<<11//0x7a<<11
|
||||
#define GET_EXPTIME_MSB_REG 27<<11//0x7b<<11
|
||||
|
||||
#define SET_GATES_LSB_REG 106<<11//0x7c<<11
|
||||
#define SET_GATES_MSB_REG 107<<11//0x7d<<11
|
||||
#define GET_GATES_LSB_REG 28<<11//0x7e<<11
|
||||
#define GET_GATES_MSB_REG 29<<11//0x7f<<11
|
||||
|
||||
#define DATA_IN_LSB_REG 30<<11
|
||||
#define DATA_IN_MSB_REG 31<<11
|
||||
|
||||
#define PATTERN_OUT_LSB_REG 32<<11
|
||||
#define PATTERN_OUT_MSB_REG 33<<11
|
||||
|
||||
#define FRAMES_FROM_START_LSB_REG 34<<11
|
||||
#define FRAMES_FROM_START_MSB_REG 35<<11
|
||||
|
||||
#define FRAMES_FROM_START_PG_LSB_REG 36<<11
|
||||
#define FRAMES_FROM_START_PG_MSB_REG 37<<11
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define PLL_PARAM_REG 80<<11//0x37<<11
|
||||
#define PLL_PARAM_OUT_REG 5<<11 //0x38<<11
|
||||
#define PLL_CNTRL_REG 81<<11//0x34<<11
|
||||
|
||||
|
||||
#ifdef NEW_GBE_INTERFACE
|
||||
#define GBE_PARAM_OUT_REG 40<<11
|
||||
#define GBE_PARAM_REG 69<<11
|
||||
#define GBE_CNTRL_REG 70<<11
|
||||
#else
|
||||
#define RX_UDP_AREG 69<<11 //rx_udpip_AReg_c : integer:= 69; *\/
|
||||
#define UDPPORTS_AREG 70<<11// udpports_AReg_c : integer:= 70; *\/
|
||||
#define RX_UDPMACL_AREG 71<<11//rx_udpmacL_AReg_c : integer:= 71; *\/
|
||||
#define RX_UDPMACH_AREG 72<<11//rx_udpmacH_AReg_c : integer:= 72; *\/
|
||||
#define DETECTORMACL_AREG 73<<11//detectormacL_AReg_c : integer:= 73; *\/
|
||||
#define DETECTORMACH_AREG 74<<11//detectormacH_AReg_c : integer:= 74; *\/
|
||||
#define DETECTORIP_AREG 75<<11//detectorip_AReg_c : integer:= 75; *\/
|
||||
#define IPCHKSUM_AREG 76<<11//ipchksum_AReg_c : integer:= 76; *\/ */
|
||||
#endif
|
||||
|
||||
|
||||
#define PATTERN_CNTRL_REG 82<<11
|
||||
#define PATTERN_LIMITS_AREG 83<<11
|
||||
|
||||
#define PATTERN_LOOP0_AREG 84<<11
|
||||
#define PATTERN_N_LOOP0_REG 85<<11
|
||||
|
||||
#define PATTERN_LOOP1_AREG 86<<11
|
||||
#define PATTERN_N_LOOP1_REG 87<<11
|
||||
|
||||
#define PATTERN_LOOP2_AREG 88<<11
|
||||
#define PATTERN_N_LOOP2_REG 89<<11
|
||||
|
||||
#define PATTERN_WAIT0_AREG 90<<11
|
||||
#define PATTERN_WAIT1_AREG 91<<11
|
||||
#define PATTERN_WAIT2_AREG 92<<11
|
||||
|
||||
|
||||
|
||||
#define DAQ_REG 93<<11
|
||||
|
||||
#define HV_REG 95<<11
|
||||
|
||||
#define PATTERN_IOCTRL_REG_LSB 108<<11
|
||||
#define PATTERN_IOCTRL_REG_MSB 109<<11
|
||||
|
||||
#define PATTERN_IOCLKCTRL_REG_LSB 110<<11
|
||||
#define PATTERN_IOCLKCTRL_REG_MSB 111<<11
|
||||
#define PATTERN_IN_REG_LSB 112<<11
|
||||
#define PATTERN_IN_REG_MSB 113<<11
|
||||
#define PATTERN_WAIT0_TIME_REG_LSB 114<<11
|
||||
#define PATTERN_WAIT0_TIME_REG_MSB 115<<11
|
||||
#define PATTERN_WAIT1_TIME_REG_LSB 116<<11
|
||||
#define PATTERN_WAIT1_TIME_REG_MSB 117<<11
|
||||
#define PATTERN_WAIT2_TIME_REG_LSB 118<<11
|
||||
#define PATTERN_WAIT2_TIME_REG_MSB 119<<11
|
||||
|
||||
//#define DAC_REG_OFF 120
|
||||
//#define DAC_0_1_VAL_REG 120<<11
|
||||
//#define DAC_2_3_VAL_REG 121<<11
|
||||
//#define DAC_4_5_VAL_REG 122<<11
|
||||
//#define DAC_6_7_VAL_REG 123<<11
|
||||
//#define DAC_8_9_VAL_REG 124<<11
|
||||
//#define DAC_10_11_VAL_REG 125<<11
|
||||
//#define DAC_12_13_VAL_REG 126<<11
|
||||
//#define DAC_14_15_VAL_REG 127<<11
|
||||
#define DAC_VAL_REG 121<<11
|
||||
#define DAC_NUM_REG 122<<11
|
||||
#define DAC_VAL_OUT_REG 42<<11
|
||||
#define ADC_LATCH_DISABLE_REG 120<<11
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* registers defined in FPGA */
|
||||
#define GAIN_REG 0
|
||||
//#define FLOW_CONTROL_REG 0x11<<11
|
||||
//#define FLOW_STATUS_REG 0x12<<11
|
||||
//#define FRAME_REG 0x13<<11
|
||||
#define MULTI_PURPOSE_REG 0
|
||||
//#define TIME_FROM_START_REG 0x16<<11
|
||||
|
||||
|
||||
#define ROI_REG 0 // 0x35<<11
|
||||
#define OVERSAMPLING_REG 0 // 0x36<<11
|
||||
#define MOENCH_CNTR_REG 0 // 0x31<<11
|
||||
#define MOENCH_CNTR_OUT_REG 0 // 0x33<<11
|
||||
#define MOENCH_CNTR_CONF_REG 0 // 0x32<<11
|
||||
|
||||
|
||||
|
||||
//image
|
||||
#define DARK_IMAGE_REG 0 // 0x81<<11
|
||||
#define GAIN_IMAGE_REG 0 // 0x82<<11
|
||||
|
||||
//counter block memory
|
||||
#define COUNTER_MEMORY_REG 0 // 0x85<<11
|
||||
|
||||
|
||||
//not used
|
||||
//#define MCB_DOUT_REG_OFF 0 // 0x200000
|
||||
//#define FIFO_CNTRL_REG_OFF 0 // 0x300000
|
||||
//#define FIFO_COUNTR_REG_OFF 0 // 0x400000
|
||||
//not used so far
|
||||
//#define SPEED_REG 0 // 0x006000
|
||||
//#define SET_NBITS_REG 0 // 0x008000
|
||||
//not used
|
||||
//#define GET_SHIFT_IN_REG 0 // 0x022000
|
||||
|
||||
|
||||
|
||||
#define SHIFTMOD 2
|
||||
#define SHIFTFIFO 9
|
||||
|
||||
/** for PCB_REV_REG */
|
||||
#define DETECTOR_TYPE_MASK 0xFF000000
|
||||
#define DETECTOR_TYPE_OFFSET 24
|
||||
#define BOARD_REVISION_MASK 0xFFFFFF
|
||||
#define MOENCH03_MODULE_ID 2
|
||||
#define JUNGFRAU_MODULE_ID 1
|
||||
#define JUNGFRAU_CTB_ID 3
|
||||
|
||||
|
||||
|
||||
|
||||
/* for control register (16bit only)*/
|
||||
#define START_ACQ_BIT 0x0001
|
||||
#define STOP_ACQ_BIT 0x0002
|
||||
#define START_FIFOTEST_BIT 0x0004 // ?????
|
||||
#define STOP_FIFOTEST_BIT 0x0008 // ??????
|
||||
#define START_READOUT_BIT 0x0010
|
||||
#define STOP_READOUT_BIT 0x0020
|
||||
#define START_EXPOSURE_BIT 0x0040
|
||||
#define STOP_EXPOSURE_BIT 0x0080
|
||||
#define START_TRAIN_BIT 0x0100
|
||||
#define STOP_TRAIN_BIT 0x0200
|
||||
#define FIFO_RESET_BIT 0x8000
|
||||
#define SYNC_RESET 0x0400
|
||||
#define GB10_RESET_BIT 0x0800
|
||||
#define MEM_RESET_BIT 0x1000
|
||||
|
||||
/* for status register */
|
||||
#define RUN_BUSY_BIT 0x00000001
|
||||
#define READOUT_BUSY_BIT 0x00000002
|
||||
#define FIFOTEST_BUSY_BIT 0x00000004 //????
|
||||
#define WAITING_FOR_TRIGGER_BIT 0x00000008
|
||||
#define DELAYBEFORE_BIT 0x00000010
|
||||
#define DELAYAFTER_BIT 0x00000020
|
||||
#define EXPOSING_BIT 0x00000040
|
||||
#define COUNT_ENABLE_BIT 0x00000080
|
||||
#define READSTATE_0_BIT 0x00000100
|
||||
#define READSTATE_1_BIT 0x00000200
|
||||
#define READSTATE_2_BIT 0x00000400
|
||||
#define LAM_BIT 0x00000400 // error!
|
||||
#define SOME_FIFO_FULL_BIT 0x00000800 // error!
|
||||
|
||||
|
||||
|
||||
#define RUNSTATE_0_BIT 0x00001000
|
||||
#define RUNSTATE_1_BIT 0x00002000
|
||||
#define RUNSTATE_2_BIT 0x00004000
|
||||
#define STOPPED_BIT 0x00008000 // stopped!
|
||||
#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
|
||||
#define RUNMACHINE_BUSY_BIT 0x00020000
|
||||
#define READMACHINE_BUSY_BIT 0x00040000
|
||||
#define PLL_RECONFIG_BUSY 0x00100000
|
||||
|
||||
|
||||
|
||||
/* for fifo status register */
|
||||
#define FIFO_ENABLED_BIT 0x80000000
|
||||
#define FIFO_DISABLED_BIT 0x01000000
|
||||
#define FIFO_ERROR_BIT 0x08000000
|
||||
#define FIFO_EMPTY_BIT 0x04000000
|
||||
#define FIFO_DATA_READY_BIT 0x02000000
|
||||
#define FIFO_COUNTER_MASK 0x000001ff
|
||||
#define FIFO_NM_MASK 0x00e00000
|
||||
#define FIFO_NM_OFF 21
|
||||
#define FIFO_NC_MASK 0x001ffe00
|
||||
#define FIFO_NC_OFF 9
|
||||
|
||||
/* for config register *///not really used yet
|
||||
#define TOT_ENABLE_BIT 0x00000002
|
||||
#define TIMED_GATE_BIT 0x00000004
|
||||
#define CONT_RO_ENABLE_BIT 0x00080000
|
||||
#define GB10_NOT_CPU_BIT 0x00001000
|
||||
|
||||
|
||||
|
||||
/* for speed register */
|
||||
#define CLK_DIVIDER_MASK 0x000000ff
|
||||
#define CLK_DIVIDER_OFFSET 0
|
||||
#define SET_LENGTH_MASK 0x00000f00
|
||||
#define SET_LENGTH_OFFSET 8
|
||||
#define WAIT_STATES_MASK 0x0000f000
|
||||
#define WAIT_STATES_OFFSET 12
|
||||
#define TOTCLK_DIVIDER_MASK 0xff000000
|
||||
#define TOTCLK_DIVIDER_OFFSET 24
|
||||
#define TOTCLK_DUTYCYCLE_MASK 0x00ff0000
|
||||
#define TOTCLK_DUTYCYCLE_OFFSET 16
|
||||
|
||||
/* for external signal register */
|
||||
#define SIGNAL_OFFSET 4
|
||||
#define SIGNAL_MASK 0xF
|
||||
#define EXT_SIG_OFF 0x0
|
||||
#define EXT_GATE_IN_ACTIVEHIGH 0x1
|
||||
#define EXT_GATE_IN_ACTIVELOW 0x2
|
||||
#define EXT_TRIG_IN_RISING 0x3
|
||||
#define EXT_TRIG_IN_FALLING 0x4
|
||||
#define EXT_RO_TRIG_IN_RISING 0x5
|
||||
#define EXT_RO_TRIG_IN_FALLING 0x6
|
||||
#define EXT_GATE_OUT_ACTIVEHIGH 0x7
|
||||
#define EXT_GATE_OUT_ACTIVELOW 0x8
|
||||
#define EXT_TRIG_OUT_RISING 0x9
|
||||
#define EXT_TRIG_OUT_FALLING 0xA
|
||||
#define EXT_RO_TRIG_OUT_RISING 0xB
|
||||
#define EXT_RO_TRIG_OUT_FALLING 0xC
|
||||
|
||||
|
||||
|
||||
/* for temperature register */
|
||||
#define T1_CLK_BIT 0x00000001
|
||||
#define T1_CS_BIT 0x00000002
|
||||
#define T2_CLK_BIT 0x00000004
|
||||
#define T2_CS_BIT 0x00000008
|
||||
|
||||
|
||||
|
||||
/* fifo control register */
|
||||
//#define FIFO_RESET_BIT 0x00000001
|
||||
//#define FIFO_DISABLE_TOGGLE_BIT 0x00000002
|
||||
|
||||
|
||||
//chip shiftin register meaning
|
||||
#define OUTMUX_OFF 20
|
||||
#define OUTMUX_MASK 0x1f
|
||||
#define PROBES_OFF 4
|
||||
#define PROBES_MASK 0x7f
|
||||
#define OUTBUF_OFF 0
|
||||
#define OUTBUF_MASK 1
|
||||
|
||||
|
||||
/* multi purpose register */
|
||||
#define PHASE_STEP_BIT 0x00000001
|
||||
#define PHASE_STEP_OFFSET 0
|
||||
// #define xxx_BIT 0x00000002
|
||||
#define RESET_COUNTER_BIT 0x00000004
|
||||
#define RESET_COUNTER_OFFSET 2
|
||||
//#define xxx_BIT 0x00000008
|
||||
//#define xxx_BIT 0x00000010
|
||||
#define SW1_BIT 0x00000020
|
||||
#define SW1_OFFSET 5
|
||||
#define WRITE_BACK_BIT 0x00000040
|
||||
#define WRITE_BACK_OFFSET 6
|
||||
#define RESET_BIT 0x00000080
|
||||
#define RESET_OFFSET 7
|
||||
#define ENET_RESETN_BIT 0x00000800
|
||||
#define ENET_RESETN_OFFSET 11
|
||||
#define INT_RSTN_BIT 0x00002000
|
||||
#define INT_RSTN_OFFSET 13
|
||||
#define DIGITAL_TEST_BIT 0x00004000
|
||||
#define DIGITAL_TEST_OFFSET 14
|
||||
//#define CHANGE_AT_POWER_ON_BIT 0x00008000
|
||||
//#define CHANGE_AT_POWER_ON_OFFSET 15
|
||||
|
||||
|
||||
/* settings/conf gain register */
|
||||
#define GAIN_MASK 0x0000000f
|
||||
#define GAIN_OFFSET 0
|
||||
#define SETTINGS_MASK 0x000000f0
|
||||
#define SETTINGS_OFFSET 4
|
||||
|
||||
|
||||
/* CHIP_OF_INTRST_REG */
|
||||
#define CHANNEL_MASK 0xffff0000
|
||||
#define CHANNEL_OFFSET 16
|
||||
#define ACTIVE_ADC_MASK 0x0000001f
|
||||
|
||||
|
||||
|
||||
/**ADC SYNC CLEAN FIFO*/
|
||||
#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
|
||||
#define CLEAN_FIFO_MASK 0x0fffff
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define PLL_CNTR_ADDR_OFF 16 //PLL_CNTR_REG bits 21 downto 16 represent the counter address
|
||||
|
||||
#define PLL_CNTR_RECONFIG_RESET_BIT 0
|
||||
#define PLL_CNTR_READ_BIT 1
|
||||
#define PLL_CNTR_WRITE_BIT 2
|
||||
#define PLL_CNTR_PLL_RESET_BIT 3
|
||||
|
||||
|
||||
#define PLL_CNTR_PHASE_EN_BIT 8
|
||||
#define PLL_CNTR_UPDN_BIT 9
|
||||
#define PLL_CNTR_CNTSEL_OFF 10
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define PLL_MODE_REG 0x0
|
||||
#define PLL_STATUS_REG 0x1
|
||||
#define PLL_START_REG 0x2
|
||||
#define PLL_N_COUNTER_REG 0x3
|
||||
#define PLL_M_COUNTER_REG 0x4
|
||||
#define PLL_C_COUNTER_REG 0x5 //which ccounter stands in param 22:18; 7:0 lowcount 15:8 highcount; 16 bypassenable; 17 oddivision
|
||||
#define PLL_PHASE_SHIFT_REG 0x6 // which ccounter stands in param 16:20; 21 updown (1 up, 0 down)
|
||||
#define PLL_K_COUNTER_REG 0x7
|
||||
#define PLL_BANDWIDTH_REG 0x8
|
||||
#define PLL_CHARGEPUMP_REG 0x9
|
||||
#define PLL_VCO_DIV_REG 0x1c
|
||||
#define PLL_MIF_REG 0x1f
|
||||
|
||||
#define PPL_M_CNT_PARAM_DEFAULT 0x4040
|
||||
#define PPL_N_CNT_PARAM_DEFAULT 0x20D0C
|
||||
#define PPL_C0_CNT_PARAM_DEFAULT 0x20D0C
|
||||
#define PPL_C1_CNT_PARAM_DEFAULT 0xA0A0
|
||||
#define PPL_C2_CNT_PARAM_DEFAULT 0x20D0C
|
||||
#define PPL_C3_CNT_PARAM_DEFAULT 0x0808
|
||||
#define PPL_BW_PARAM_DEFAULT 0x2EE0
|
||||
#define PPL_VCO_PARAM_DEFAULT 0x1
|
||||
|
||||
#define NEW_PLL_RECONFIG
|
||||
|
||||
#ifdef NEW_PLL_RECONFIG
|
||||
#define PLL_VCO_FREQ_MHZ 400//480//800
|
||||
#else
|
||||
#define PLL_VCO_FREQ_MHZ 480//800
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
GBE parameter and control registers definitions
|
||||
*/
|
||||
|
||||
#define GBE_CTRL_WSTROBE 0
|
||||
#define GBE_CTRL_VAR_OFFSET 16
|
||||
#define GBE_CTRL_VAR_MASK 0XF
|
||||
#define GBE_CTRL_RAMADDR_OFFSET 24
|
||||
#define GBE_CTRL_RAMADDR_MASK 0X3F
|
||||
#define GBE_CTRL_INTERFACE 23
|
||||
|
||||
#define RX_UDP_IP_ADDR 0
|
||||
#define RX_UDP_PORTS_ADDR 1
|
||||
#define RX_UDP_MAC_L_ADDR 2
|
||||
#define RX_UDP_MAC_H_ADDR 3
|
||||
#define IPCHECKSUM_ADDR 4
|
||||
#define GBE_DELAY_ADDR 5
|
||||
#define GBE_RESERVED1_ADDR 6
|
||||
#define GBE_RESERVED2_ADDR 7
|
||||
#define DETECTOR_MAC_L_ADDR 8
|
||||
#define DETECTOR_MAC_H_ADDR 9
|
||||
#define DETECTOR_IP_ADDR 10
|
||||
|
||||
|
||||
|
||||
/**------------------
|
||||
-- pattern registers definitions
|
||||
--------------------------------------------- */
|
||||
#define IOSIGNALS_MASK 0xfffffffffffff
|
||||
#define ADC_ENABLE_BIT 63
|
||||
#define APATTERN_MASK 0xffff
|
||||
#define ASTART_OFFSET 0
|
||||
#define ASTOP_OFFSET 16
|
||||
#define PATTERN_CTRL_WRITE_BIT 0
|
||||
#define PATTERN_CTRL_READ_BIT 1
|
||||
#define PATTERN_CTRL_ADDR_OFFSET 16
|
||||
#define MAX_PATTERN_LENGTH 1024
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
139
slsDetectorSoftware/jctbDetectorServer/server.c
Executable file
139
slsDetectorSoftware/jctbDetectorServer/server.c
Executable file
@ -0,0 +1,139 @@
|
||||
/* A simple server in the internet domain using TCP
|
||||
The port number is passed as an argument */
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "communication_funcs.h"
|
||||
#include "server_funcs.h"
|
||||
#include <string.h>
|
||||
|
||||
|
||||
|
||||
extern int sockfd;
|
||||
extern int phase_shift;
|
||||
|
||||
|
||||
|
||||
void error(char *msg)
|
||||
{
|
||||
perror(msg);
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int portno, b;
|
||||
char cmd[500];
|
||||
int retval=OK;
|
||||
int sd, fd;
|
||||
int iarg;
|
||||
int checkType = 1;
|
||||
|
||||
|
||||
for(iarg=1; iarg<argc; iarg++){
|
||||
|
||||
if(!strcasecmp(argv[iarg],"-phaseshift")){
|
||||
if(argc==iarg+1){
|
||||
printf("No phaseshift given. Exiting.\n");
|
||||
return 1;
|
||||
}
|
||||
if ( sscanf(argv[iarg+1],"%d",&phase_shift)==0) {
|
||||
printf("could not decode phase shift\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
else if(!strcasecmp(argv[iarg],"-test")){
|
||||
if(argc==iarg+1){
|
||||
printf("No test condition given. Exiting.\n");
|
||||
return 1;
|
||||
}
|
||||
if(!strcasecmp(argv[iarg+1],"with_gotthard")){
|
||||
checkType = 0;
|
||||
}else{
|
||||
printf("could not decode test condition. Possible arguments: with_gotthard. Exiting\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//stop server
|
||||
if ((argc > 2) && (!strcasecmp(argv[2],"stopserver"))){
|
||||
portno = DEFAULT_PORTNO+1;
|
||||
if ( sscanf(argv[1],"%d",&portno) ==0) {
|
||||
printf("could not open stop server: unknown port\n");
|
||||
return 1;
|
||||
}
|
||||
b=0;
|
||||
printf("\n\nStop Server\nOpening stop server on port %d\n",portno);
|
||||
checkType=0;
|
||||
|
||||
}
|
||||
|
||||
//control server
|
||||
else {
|
||||
portno = DEFAULT_PORTNO;
|
||||
if(checkType)
|
||||
sprintf(cmd,"%s %d stopserver &",argv[0],DEFAULT_PORTNO+1);
|
||||
else
|
||||
sprintf(cmd,"%s %d stopserver -test with_gotthard &",argv[0],DEFAULT_PORTNO+1);
|
||||
printf("\n\nControl Server\nOpening control server on port %d\n",portno );
|
||||
|
||||
//printf("\n\ncmd:%s\n",cmd);
|
||||
system(cmd);
|
||||
b=1;
|
||||
checkType=1;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
init_detector(b, checkType);
|
||||
|
||||
|
||||
sd=bindSocket(portno);
|
||||
sockfd=sd;
|
||||
if (getServerError(sd)) {
|
||||
printf("server error!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* assign function table */
|
||||
function_table();
|
||||
#ifdef VERBOSE
|
||||
printf("function table assigned \n");
|
||||
#endif
|
||||
|
||||
|
||||
/* waits for connection */
|
||||
while(retval!=GOODBYE) {
|
||||
#ifdef VERBOSE
|
||||
printf("\n");
|
||||
#endif
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Waiting for client call\n");
|
||||
#endif
|
||||
fd=acceptConnection(sockfd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Conenction accepted\n");
|
||||
#endif
|
||||
retval=decode_function(fd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("function executed\n");
|
||||
#endif
|
||||
closeConnection(fd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("connection closed\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
exitServer(sockfd);
|
||||
printf("Goodbye!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
78
slsDetectorSoftware/jctbDetectorServer/server_defs.h
Executable file
78
slsDetectorSoftware/jctbDetectorServer/server_defs.h
Executable file
@ -0,0 +1,78 @@
|
||||
#ifndef SERVER_DEFS_H
|
||||
#define SERVER_DEFS_H
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
// Hardware definitions
|
||||
#define NMAXMODY 1
|
||||
#define NMAXMOD (NMAXMODX*NMAXMODY)
|
||||
|
||||
#define NCHAN 32
|
||||
#define NCHIP 1
|
||||
#define NADC 1
|
||||
|
||||
#ifdef CTB
|
||||
#define NDAC 24
|
||||
#define NPWR 5
|
||||
#else
|
||||
#define NDAC 16
|
||||
#define NPWR 0
|
||||
#endif
|
||||
#define DAC_CMD_OFF 20
|
||||
|
||||
#define NMAXMODX 1
|
||||
#define NCHANS (NCHAN*NCHIP*NMAXMOD)
|
||||
#define NDACS (NDAC*NMAXMOD)
|
||||
|
||||
#define JUNGFRAU_NCHAN (256*256)
|
||||
#define JUNGFRAU_NCHIP 8
|
||||
#define JUNGFRAU_NADC 0
|
||||
#define JUNGFRAU_NDAC 16
|
||||
#define JUNGFRAU_NCHANS (JUNGFRAU_NCHAN*JUNGFRAU_NCHIP*NMAXMOD)
|
||||
|
||||
|
||||
|
||||
/**when moench readout tested with gotthard module*/
|
||||
#define GOTTHARDNCHAN 128
|
||||
#define GOTTHARDNCHIP 10
|
||||
|
||||
|
||||
#define NTRIMBITS 6
|
||||
#define NCOUNTBITS 24
|
||||
|
||||
#define NCHIPS_PER_ADC 2
|
||||
|
||||
//#define TRIM_DR ((2**NTRIMBITS)-1)
|
||||
//#define COUNT_DR ((2**NCOUNTBITS)-1)
|
||||
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
|
||||
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
|
||||
|
||||
|
||||
#define ALLMOD 0xffff
|
||||
#define ALLFIFO 0xffff
|
||||
|
||||
#define GOTTHARD_ADCSYNC_VAL 0x32214
|
||||
#define ADCSYNC_VAL 0x02111
|
||||
#define TOKEN_RESTART_DELAY 0x88000000
|
||||
#define TOKEN_RESTART_DELAY_ROI 0x1b000000
|
||||
#define TOKEN_TIMING_REV1 0x1f16
|
||||
#define TOKEN_TIMING_REV2 0x1f0f
|
||||
|
||||
#define DEFAULT_PHASE_SHIFT 0 // 120
|
||||
#define DEFAULT_IP_PACKETSIZE 0x0522
|
||||
#define DEFAULT_UDP_PACKETSIZE 0x050E
|
||||
#define ADC1_IP_PACKETSIZE 256*2+14+20
|
||||
#define ADC1_UDP_PACKETSIZE 256*2+4+8+2
|
||||
|
||||
#ifdef VIRTUAL
|
||||
#define DEBUGOUT
|
||||
#endif
|
||||
|
||||
#define CLK_FREQ 156.25E+6
|
||||
#define ADC_CLK_FREQ 32E+6
|
||||
|
||||
|
||||
#endif
|
||||
3513
slsDetectorSoftware/jctbDetectorServer/server_funcs.c
Executable file
3513
slsDetectorSoftware/jctbDetectorServer/server_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
98
slsDetectorSoftware/jctbDetectorServer/server_funcs.h
Executable file
98
slsDetectorSoftware/jctbDetectorServer/server_funcs.h
Executable file
@ -0,0 +1,98 @@
|
||||
#ifndef SERVER_FUNCS_H
|
||||
#define SERVER_FUNCS_H
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
/*
|
||||
#include <sys/types.h>
|
||||
#include <sys/socket.h>
|
||||
#include <netinet/in.h>
|
||||
*/
|
||||
#include "communication_funcs.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#define GOODBYE -200
|
||||
|
||||
int sockfd;
|
||||
|
||||
int function_table();
|
||||
|
||||
int decode_function(int);
|
||||
int init_detector(int,int);
|
||||
|
||||
int M_nofunc(int);
|
||||
int exit_server(int);
|
||||
|
||||
|
||||
|
||||
|
||||
// General purpose functions
|
||||
int get_detector_type(int);
|
||||
int set_number_of_modules(int);
|
||||
int get_max_number_of_modules(int);
|
||||
|
||||
|
||||
int exec_command(int);
|
||||
int set_external_signal_flag(int);
|
||||
int set_external_communication_mode(int);
|
||||
int get_id(int);
|
||||
int digital_test(int);
|
||||
int write_register(int);
|
||||
int read_register(int);
|
||||
int set_dac(int);
|
||||
int get_adc(int);
|
||||
int set_channel(int);
|
||||
int set_chip(int);
|
||||
int set_module(int);
|
||||
int get_channel(int);
|
||||
int get_chip(int);
|
||||
int get_module(int);
|
||||
|
||||
int get_threshold_energy(int);
|
||||
int set_threshold_energy(int);
|
||||
int set_settings(int);
|
||||
int start_acquisition(int);
|
||||
int stop_acquisition(int);
|
||||
int start_readout(int);
|
||||
int get_run_status(int);
|
||||
int read_frame(int);
|
||||
int read_all(int);
|
||||
int start_and_read_all(int);
|
||||
int set_timer(int);
|
||||
int get_time_left(int);
|
||||
int set_dynamic_range(int);
|
||||
int set_roi(int);
|
||||
int get_roi(int);
|
||||
int set_speed(int);
|
||||
int set_readout_flags(int);
|
||||
int execute_trimming(int);
|
||||
int lock_server(int);
|
||||
int set_port(int);
|
||||
int get_last_client_ip(int);
|
||||
int set_master(int);
|
||||
int set_synchronization(int);
|
||||
|
||||
int update_client(int);
|
||||
int send_update(int);
|
||||
int configure_mac(int);
|
||||
|
||||
int load_image(int);
|
||||
int read_counter_block(int);
|
||||
int reset_counter_block(int);
|
||||
|
||||
int start_receiver(int);
|
||||
int stop_receiver(int);
|
||||
|
||||
|
||||
int calibrate_pedestal(int);
|
||||
|
||||
int set_roi(int);
|
||||
int set_ctb_pattern(int);
|
||||
|
||||
int write_adc_register(int);;
|
||||
#endif
|
||||
39
slsDetectorSoftware/jctbDetectorServer/sharedmemory.c
Executable file
39
slsDetectorSoftware/jctbDetectorServer/sharedmemory.c
Executable file
@ -0,0 +1,39 @@
|
||||
#include "sharedmemory.h"
|
||||
|
||||
struct statusdata *stdata;
|
||||
|
||||
int inism(int clsv) {
|
||||
|
||||
static int scansmid;
|
||||
|
||||
if (clsv==SMSV) {
|
||||
if ( (scansmid=shmget(SMKEY,1024,IPC_CREAT | 0666 ))==-1 ) {
|
||||
return -1;
|
||||
}
|
||||
if ( (stdata=shmat(scansmid,NULL,0))==(void*)-1) {
|
||||
return -2;
|
||||
}
|
||||
}
|
||||
|
||||
if (clsv==SMCL) {
|
||||
if ( (scansmid=shmget(SMKEY,0,0) )==-1 ) {
|
||||
return -3;
|
||||
}
|
||||
if ( (stdata=shmat(scansmid,NULL,0))==(void*)-1) {
|
||||
return -4;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
void write_status_sm(char *status) {
|
||||
strcpy(stdata->status,status);
|
||||
}
|
||||
|
||||
void write_stop_sm(int v) {
|
||||
stdata->stop=v;
|
||||
}
|
||||
|
||||
void write_runnumber_sm(int v) {
|
||||
stdata->runnumber=v;
|
||||
}
|
||||
48
slsDetectorSoftware/jctbDetectorServer/sharedmemory.h
Executable file
48
slsDetectorSoftware/jctbDetectorServer/sharedmemory.h
Executable file
@ -0,0 +1,48 @@
|
||||
#ifndef SM
|
||||
#define SM
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdarg.h>
|
||||
#include <unistd.h>
|
||||
//#include <asm/page.h>
|
||||
#include <sys/mman.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdarg.h>
|
||||
#include <unistd.h>
|
||||
|
||||
|
||||
#include <sys/shm.h>
|
||||
|
||||
#include <sys/ipc.h>
|
||||
#include <sys/stat.h>
|
||||
|
||||
/* key for shared memory */
|
||||
#define SMKEY 10001
|
||||
|
||||
#define SMSV 1
|
||||
#define SMCL 2
|
||||
|
||||
|
||||
struct statusdata {
|
||||
int runnumber;
|
||||
int stop;
|
||||
char status[20];
|
||||
} ;
|
||||
|
||||
|
||||
/* for shared memory */
|
||||
|
||||
int inism(int clsv);
|
||||
void write_status_sm(char *status);
|
||||
void write_stop_sm(int v);
|
||||
void write_runnumber_sm(int v);
|
||||
|
||||
#endif
|
||||
1
slsDetectorSoftware/jctbDetectorServer/sls_detector_defs.h
Symbolic link
1
slsDetectorSoftware/jctbDetectorServer/sls_detector_defs.h
Symbolic link
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_defs.h
|
||||
1
slsDetectorSoftware/jctbDetectorServer/sls_detector_funcs.h
Symbolic link
1
slsDetectorSoftware/jctbDetectorServer/sls_detector_funcs.h
Symbolic link
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_funcs.h
|
||||
1
slsDetectorSoftware/jctbDetectorServer/sls_receiver_defs.h
Symbolic link
1
slsDetectorSoftware/jctbDetectorServer/sls_receiver_defs.h
Symbolic link
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_defs.h
|
||||
1
slsDetectorSoftware/jctbDetectorServer/sls_receiver_funcs.h
Symbolic link
1
slsDetectorSoftware/jctbDetectorServer/sls_receiver_funcs.h
Symbolic link
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_funcs.h
|
||||
46
slsDetectorSoftware/jctbDetectorServer/stop_server.c
Executable file
46
slsDetectorSoftware/jctbDetectorServer/stop_server.c
Executable file
@ -0,0 +1,46 @@
|
||||
/* A simple server in the internet domain using TCP
|
||||
The port number is passed as an argument */
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
#include "communication_funcs.h"
|
||||
#include "firmware_funcs.h"
|
||||
|
||||
|
||||
int sockfd;
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int portno;
|
||||
int retval=0;
|
||||
|
||||
portno = DEFAULT_PORTNO;
|
||||
|
||||
|
||||
bindSocket(portno);
|
||||
if (getServerError())
|
||||
return -1;
|
||||
|
||||
|
||||
|
||||
/* waits for connection */
|
||||
while(retval!=GOODBYE) {
|
||||
#ifdef VERBOSE
|
||||
printf("\n");
|
||||
#endif
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Stop server: waiting for client call\n");
|
||||
#endif
|
||||
acceptConnection();
|
||||
retval=stopStateMachine();
|
||||
closeConnection();
|
||||
}
|
||||
|
||||
exitServer();
|
||||
printf("Goodbye!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user