diff --git a/slsDetectorServers/ctbDetectorServer/gitInfo.txt b/slsDetectorServers/ctbDetectorServer/gitInfo.txt index d57e03620..39e9b58b8 100644 --- a/slsDetectorServers/ctbDetectorServer/gitInfo.txt +++ b/slsDetectorServers/ctbDetectorServer/gitInfo.txt @@ -1,9 +1,9 @@ Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git -Repsitory UUID: 08bd2378f4956ea9a0b75381872854b3b129288f -Revision: 32 +Repsitory UUID: ceb515d517baf2a6e3590013fd7550186d2906b8 +Revision: 33 Branch: refactor -Last Changed Author: Dhanya_Thattil -Last Changed Rev: 4372 -Last Changed Date: 2019-03-04 17:47:37.000000002 +0100 ./RegisterDefs.h +Last Changed Author: GitHub_GitHub +Last Changed Rev: 4377 +Last Changed Date: 2019-03-06 09:17:39.000000002 +0100 ./RegisterDefs.h diff --git a/slsDetectorServers/ctbDetectorServer/gitInfoCtb.h b/slsDetectorServers/ctbDetectorServer/gitInfoCtb.h index 9e94d5d0d..714bec21f 100644 --- a/slsDetectorServers/ctbDetectorServer/gitInfoCtb.h +++ b/slsDetectorServers/ctbDetectorServer/gitInfoCtb.h @@ -1,6 +1,6 @@ #define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git" -#define GITREPUUID "08bd2378f4956ea9a0b75381872854b3b129288f" -#define GITAUTH "Dhanya_Thattil" -#define GITREV 0x4372 -#define GITDATE 0x20190304 +#define GITREPUUID "ceb515d517baf2a6e3590013fd7550186d2906b8" +#define GITAUTH "GitHub_GitHub" +#define GITREV 0x4377 +#define GITDATE 0x20190306 #define GITBRANCH "refactor" diff --git a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c index 59c1c134d..106057039 100644 --- a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c @@ -783,20 +783,20 @@ void setSpeed(enum speedVariable ind, int val) { switch(ind) { case ADC_PHASE: case PHASE_SHIFT: - FILE_LOG(logINFO, ("Configuring ADC Phase\n")); + FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n")); configurePhase(RUN_CLK, val); break; case DBIT_PHASE: - FILE_LOG(logINFO, ("Configuring Dbit Phase\n")); + FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n")); configurePhase(DBIT_CLK, val); break; case ADC_CLOCK: - FILE_LOG(logINFO, ("Configuring ADC Clock\n")); + FILE_LOG(logINFOBLUE, ("Configuring ADC Clock\n")); configureFrequency(ADC_CLK, val); configureSyncFrequency(ADC_CLK); break; case DBIT_CLOCK: - FILE_LOG(logINFO, ("Configuring Dbit Clock\n")); + FILE_LOG(logINFOBLUE, ("Configuring Dbit Clock\n")); configureFrequency(DBIT_CLK, val); configureSyncFrequency(DBIT_CLK); break; @@ -807,7 +807,7 @@ void setSpeed(enum speedVariable ind, int val) { setAdcOffsetRegister(0, val); break; case CLOCK_DIVIDER: - FILE_LOG(logINFO, ("Configuring Run Clock\n")); + FILE_LOG(logINFOBLUE, ("Configuring Run Clock\n")); configureFrequency(RUN_CLK, val); configureSyncFrequency(RUN_CLK); break; @@ -822,7 +822,7 @@ int getSpeed(enum speedVariable ind) { case PHASE_SHIFT: return getPhase(RUN_CLK); case DBIT_PHASE: - return clkPhase[DBIT_CLK]; + return getPhase(DBIT_CLK); case ADC_CLOCK: return getFrequency(ADC_CLK); case DBIT_CLOCK: @@ -913,15 +913,6 @@ int64_t setTimer(enum timerIndex ind, int64_t val) { if(val >= 0){ FILE_LOG(logINFO, ("Setting period: %lldns\n",(long long int)val)); val *= (1E-3 * clkDivider[ADC_CLK]); - // make period odd - //FIXME to be tested - /*if (val % 2 == 0) { //fIXME: period is even here, not other way round? - FILE_LOG(logINFO, ("\tPeriod %lld not even, adding 1\n", (long long int)val)); - ++val; - FILE_LOG(logINFO, ("\tNew Period:%lld\n", (long long int)val)) - } else { - FILE_LOG(logINFO, ("\tPeriod already even:%lld\n", (long long int)val)) - }*/ } retval = set64BitReg(val, PERIOD_LSB_REG, PERIOD_MSB_REG )/ (1E-3 * clkDivider[ADC_CLK]); FILE_LOG(logINFO, ("\tGetting period: %lldns\n", (long long int)retval)); @@ -1027,11 +1018,14 @@ int validateTimer(enum timerIndex ind, int64_t val, int64_t retval) { case FRAME_PERIOD: case DELAY_AFTER_TRIGGER: // convert to freq - val *= (1E-3 * ADC_CLK); + val *= (1E-3 * clkDivider[ADC_CLK]); // convert back to timer - val = (val) / (1E-3 * ADC_CLK); - if (val != retval) - return FAIL; + val = (val) / (1E-3 * clkDivider[ADC_CLK]); + if (val != retval) { + FILE_LOG(logERROR, ("Could not validate timer %d. Set %lld, got %lld\n", + (long long unsigned int)val, (long long unsigned int)retval)); + return FAIL; + } break; default: break; @@ -1621,12 +1615,13 @@ int enableTenGigabitEthernet(int val) { // ind can only be ADC_CLK or DBIT_CLK void configurePhase(enum CLKINDEX ind, int val) { + char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"}; if (val > 65535 || val < -65535) { - FILE_LOG(logERROR, ("\tPhase provided outside limits\n")); + FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind])); return; } - FILE_LOG(logINFO, ("Configuring Phase of C%d to %d\n", ind, val)); + FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val)); // reset only pll ALTERA_PLL_ResetPLL(); @@ -1655,10 +1650,11 @@ int getPhase(enum CLKINDEX ind) { } void configureFrequency(enum CLKINDEX ind, int val) { - if (val < 0) + char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"}; + if (val <= 0) return; - FILE_LOG(logINFO, ("\tConfiguring Frequency of C%d to %d MHz\n", ind, val)); + FILE_LOG(logINFO, ("\tConfiguring Frequency of C%d(%s) to %d MHz\n", ind, clock_names[ind], val)); // check adc clk too high if (ind == ADC_CLK && val > MAXIMUM_ADC_CLK) { @@ -1668,7 +1664,7 @@ void configureFrequency(enum CLKINDEX ind, int val) { // Calculate and set output frequency clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val); - FILE_LOG(logINFO, ("\tC%d: Frequency set to %d MHz\n", ind, clkDivider[ind])); + FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind])); } int getFrequency(enum CLKINDEX ind) { @@ -1676,17 +1672,18 @@ int getFrequency(enum CLKINDEX ind) { } void configureSyncFrequency(enum CLKINDEX ind) { + char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"}; int clka = 0, clkb = 0; switch(ind) { - case ADC_CLOCK: + case ADC_CLK: clka = DBIT_CLK; clkb = RUN_CLK; break; - case DBIT_CLOCK: + case DBIT_CLK: clka = ADC_CLK; clkb = RUN_CLK; break; - case CLOCK_DIVIDER: + case RUN_CLK: clka = DBIT_CLK; clkb = ADC_CLK; break; @@ -1694,19 +1691,24 @@ void configureSyncFrequency(enum CLKINDEX ind) { return; } - int clksync = getFrequency(SYNC_CLK); + int syncFreq = getFrequency(SYNC_CLK); int retval = getFrequency(ind); + int aFreq = getFrequency(clka); + int bFreq = getFrequency(clkb); + FILE_LOG(logDEBUG1, ("Sync Frequncy:%d, RetvalFreq(%s):%d, aFreq(%s):%d, bFreq(%s):%d\n", + syncFreq, clock_names[ind], retval, clock_names[clka], aFreq, clock_names[clkb], bFreq)); + int configure = 0; // sync is greater than current - if (clksync > retval) { - FILE_LOG(logINFO, ("\t--Configuring Sync Clock\n")); + if (syncFreq > retval) { + FILE_LOG(logINFO, ("\t--Configuring Sync Clock\n"));cprintf(BG_RED, "SETTING SYNC CLOCK!!!"); configure = 1; } // the others are both greater than current - else if ((clka > retval && clkb > retval)) { - FILE_LOG(logINFO, ("\t++Configuring Sync Clock\n")); + else if ((aFreq > retval && bFreq > retval)) { + FILE_LOG(logINFO, ("\t++Configuring Sync Clock\n"));cprintf(BG_RED, "\n\nSETTING SYNC CLOCK!!!\n\n"); configure = 1; } @@ -1783,6 +1785,7 @@ uint64_t readPatternWord(int addr) { // unset read strobe bus_w(reg, bus_r(reg) & (~PATTERN_CNTRL_RD_MSK)); + usleep(WAIT_TIME_PATTERN_READ); // read value uint64_t retval = get64BitReg(PATTERN_OUT_LSB_REG, PATTERN_OUT_MSB_REG); @@ -2181,12 +2184,14 @@ enum runStatus getRunStatus(){ return TRANSMITTING; } + + /* until Carlos updates firmware if (digitalEnable && !analogEnable) { if (retval & STATUS_ALL_FF_EMPTY_MSK) { FILE_LOG(logINFOBLUE, ("Status: Transmitting (All fifo empty)\n")); return TRANSMITTING; } - } + }*/ if (! (retval & STATUS_IDLE_MSK)) { FILE_LOG(logINFOBLUE, ("Status: Idle\n")); diff --git a/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h index dd0dfd9e4..317fa3c99 100644 --- a/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h +++ b/slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h @@ -85,6 +85,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, #define WAIT_TIME_US_PLL (10 * 1000) #define WAIT_TIME_US_STP_ACQ (100) #define WAIT_TIME_CONFIGURE_MAC (500 * 1000) +#define WAIT_TIME_PATTERN_READ (10) /* MSB & LSB DEFINES */ #define MSB_OF_64_BIT_REG_OFST (32) diff --git a/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c index 4e3f6044c..41f89ff6c 100644 --- a/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c @@ -764,20 +764,20 @@ void setSpeed(enum speedVariable ind, int val) { switch(ind) { case ADC_PHASE: case PHASE_SHIFT: - FILE_LOG(logINFO, ("Configuring ADC Phase\n")); + FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n")); configurePhase(RUN_CLK, val); break; case DBIT_PHASE: - FILE_LOG(logINFO, ("Configuring Dbit Phase\n")); + FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n")); configurePhase(DBIT_CLK, val); break; case ADC_CLOCK: - FILE_LOG(logINFO, ("Configuring ADC Clock\n")); + FILE_LOG(logINFOBLUE, ("Configuring ADC Clock\n")); configureFrequency(ADC_CLK, val); configureSyncFrequency(ADC_CLK); break; case DBIT_CLOCK: - FILE_LOG(logINFO, ("Configuring Dbit Clock\n")); + FILE_LOG(logINFOBLUE, ("Configuring Dbit Clock\n")); configureFrequency(DBIT_CLK, val); configureSyncFrequency(DBIT_CLK); break; @@ -788,7 +788,7 @@ void setSpeed(enum speedVariable ind, int val) { setAdcOffsetRegister(0, val); break; case CLOCK_DIVIDER: - FILE_LOG(logINFO, ("Configuring Run Clock\n")); + FILE_LOG(logINFOBLUE, ("Configuring Run Clock\n")); configureFrequency(RUN_CLK, val); configureSyncFrequency(RUN_CLK); break; @@ -803,7 +803,7 @@ int getSpeed(enum speedVariable ind) { case PHASE_SHIFT: return getPhase(RUN_CLK); case DBIT_PHASE: - return clkPhase[DBIT_CLK]; + return getPhase(DBIT_CLK); case ADC_CLOCK: return getFrequency(ADC_CLK); case DBIT_CLOCK: @@ -1007,11 +1007,14 @@ int validateTimer(enum timerIndex ind, int64_t val, int64_t retval) { case FRAME_PERIOD: case DELAY_AFTER_TRIGGER: // convert to freq - val *= (1E-3 * ADC_CLK); + val *= (1E-3 * clkDivider[ADC_CLK]); // convert back to timer - val = (val) / (1E-3 * ADC_CLK); - if (val != retval) - return FAIL; + val = (val) / (1E-3 * clkDivider[ADC_CLK]); + if (val != retval) { + FILE_LOG(logERROR, ("Could not validate timer %d. Set %lld, got %lld\n", + (long long unsigned int)val, (long long unsigned int)retval)); + return FAIL; + } break; default: break; @@ -1314,12 +1317,13 @@ int powerChip(int on) { // ind can only be ADC_CLK or DBIT_CLK void configurePhase(enum CLKINDEX ind, int val) { + char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"}; if (val > 65535 || val < -65535) { - FILE_LOG(logERROR, ("\tPhase provided outside limits\n")); + FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind])); return; } - FILE_LOG(logINFO, ("Configuring Phase of C%d to %d\n", ind, val)); + FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val)); // reset only pll ALTERA_PLL_ResetPLL(); @@ -1348,10 +1352,11 @@ int getPhase(enum CLKINDEX ind) { } void configureFrequency(enum CLKINDEX ind, int val) { - if (val < 0) + char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"}; + if (val <= 0) return; - FILE_LOG(logINFO, ("\tConfiguring Frequency of C%d to %d MHz\n", ind, val)); + FILE_LOG(logINFO, ("\tConfiguring Frequency of C%d(%s) to %d MHz\n", ind, clock_names[ind], val)); // check adc clk too high if (ind == ADC_CLK && val > MAXIMUM_ADC_CLK) { @@ -1361,7 +1366,7 @@ void configureFrequency(enum CLKINDEX ind, int val) { // Calculate and set output frequency clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val); - FILE_LOG(logINFO, ("\tC%d: Frequency set to %d MHz\n", ind, clkDivider[ind])); + FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind])); } int getFrequency(enum CLKINDEX ind) { @@ -1369,17 +1374,18 @@ int getFrequency(enum CLKINDEX ind) { } void configureSyncFrequency(enum CLKINDEX ind) { + char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"}; int clka = 0, clkb = 0; switch(ind) { - case ADC_CLOCK: + case ADC_CLK: clka = DBIT_CLK; clkb = RUN_CLK; break; - case DBIT_CLOCK: + case DBIT_CLK: clka = ADC_CLK; clkb = RUN_CLK; break; - case CLOCK_DIVIDER: + case RUN_CLK: clka = DBIT_CLK; clkb = ADC_CLK; break; @@ -1387,19 +1393,24 @@ void configureSyncFrequency(enum CLKINDEX ind) { return; } - int clksync = getFrequency(SYNC_CLK); + int syncFreq = getFrequency(SYNC_CLK); int retval = getFrequency(ind); + int aFreq = getFrequency(clka); + int bFreq = getFrequency(clkb); + FILE_LOG(logDEBUG1, ("Sync Frequncy:%d, RetvalFreq(%s):%d, aFreq(%s):%d, bFreq(%s):%d\n", + syncFreq, clock_names[ind], retval, clock_names[clka], aFreq, clock_names[clkb], bFreq)); + int configure = 0; // sync is greater than current - if (clksync > retval) { - FILE_LOG(logINFO, ("\t--Configuring Sync Clock\n")); + if (syncFreq > retval) { + FILE_LOG(logINFO, ("\t--Configuring Sync Clock\n"));cprintf(BG_RED, "SETTING SYNC CLOCK!!!"); configure = 1; } // the others are both greater than current - else if ((clka > retval && clkb > retval)) { - FILE_LOG(logINFO, ("\t++Configuring Sync Clock\n")); + else if ((aFreq > retval && bFreq > retval)) { + FILE_LOG(logINFO, ("\t++Configuring Sync Clock\n"));cprintf(BG_RED, "\n\nSETTING SYNC CLOCK!!!\n\n"); configure = 1; } @@ -1408,6 +1419,7 @@ void configureSyncFrequency(enum CLKINDEX ind) { configureFrequency(SYNC_CLK, retval); } + void setAdcOffsetRegister(int adc, int val) { if (val < 0) return; @@ -1475,6 +1487,7 @@ uint64_t readPatternWord(int addr) { // unset read strobe bus_w(reg, bus_r(reg) & (~PATTERN_CNTRL_RD_MSK)); + usleep(WAIT_TIME_PATTERN_READ); // read value uint64_t retval = get64BitReg(PATTERN_OUT_LSB_REG, PATTERN_OUT_MSB_REG); @@ -1872,12 +1885,13 @@ enum runStatus getRunStatus(){ return TRANSMITTING; } - if (digitalEnable && !analogEnable) { - if (retval & STATUS_ALL_FF_EMPTY_MSK) { - FILE_LOG(logINFOBLUE, ("Status: Transmitting (All fifo empty)\n")); - return TRANSMITTING; - } - } + /* until Carlos updates firmware + if (digitalEnable && !analogEnable) { + if (retval & STATUS_ALL_FF_EMPTY_MSK) { + FILE_LOG(logINFOBLUE, ("Status: Transmitting (All fifo empty)\n")); + return TRANSMITTING; + } + }*/ if (! (retval & STATUS_IDLE_MSK)) { FILE_LOG(logINFOBLUE, ("Status: Idle\n")); diff --git a/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h index dbcec5e4f..51d528ddb 100644 --- a/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h +++ b/slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h @@ -68,6 +68,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7}; #define WAIT_TIME_US_PLL (10 * 1000) #define WAIT_TIME_US_STP_ACQ (100) #define WAIT_TIME_CONFIGURE_MAC (500 * 1000) +#define WAIT_TIME_PATTERN_READ (10) /* MSB & LSB DEFINES */ #define MSB_OF_64_BIT_REG_OFST (32) diff --git a/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h b/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h index 4ef45a2d5..b807ba220 100755 --- a/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h +++ b/slsDetectorServers/slsDetectorServer/ALTERA_PLL.h @@ -107,9 +107,13 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32 void ALTERA_PLL_ResetPLL () { FILE_LOG(logINFO, ("Resetting only PLL\n")); + FILE_LOG(logDEBUG2, ("pllrstmsk:0x%x\n", ALTERA_PLL_Cntrl_PLLRstMask)); + bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask); + FILE_LOG(logDEBUG2, ("Set PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg))); usleep(ALTERA_PLL_WAIT_TIME_US); bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask); + FILE_LOG(logDEBUG2, ("UnSet PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg))); } @@ -131,19 +135,28 @@ void ALTERA_PLL_ResetPLLAndReconfiguration () { * @param val value */ void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val) { - FILE_LOG(logINFO, ("Setting PLL Reconfig Reg\n")); + FILE_LOG(logINFO, ("Setting PLL Reconfig Reg, reg:0x%x, val:0x%x)\n", reg, val)); + + FILE_LOG(logDEBUG2, ("pllparamreg:0x%x pllcontrolreg:0x%x addrofst:%d addrmsk:0x%x wrmask:0x%x\n", + ALTERA_PLL_Param_Reg, ALTERA_PLL_Cntrl_Reg, ALTERA_PLL_Cntrl_AddrOfst, ALTERA_PLL_Cntrl_AddrMask, ALTERA_PLL_Cntrl_WrPrmtrMask)); // set parameter bus_w(ALTERA_PLL_Param_Reg, val); + FILE_LOG(logDEBUG2, ("Set Parameter: ALTERA_PLL_Param_Reg:0x%x\n", bus_r(ALTERA_PLL_Param_Reg))); + usleep(ALTERA_PLL_WAIT_TIME_US); // set address bus_w(ALTERA_PLL_Cntrl_Reg, (reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask); + FILE_LOG(logDEBUG2, ("Set Address: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg))); usleep(ALTERA_PLL_WAIT_TIME_US); //write parameter bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_WrPrmtrMask); + FILE_LOG(logDEBUG2, ("Set WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg))); bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_WrPrmtrMask); usleep(ALTERA_PLL_WAIT_TIME_US); + FILE_LOG(logDEBUG2, ("Unset WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg))); + usleep(ALTERA_PLL_WAIT_TIME_US); } /** @@ -162,7 +175,6 @@ void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) { // write phase shift ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value); - usleep(ALTERA_PLL_WAIT_TIME_US); } /** @@ -171,7 +183,6 @@ void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) { void ALTERA_PLL_SetModePolling() { FILE_LOG(logINFO, ("\tSetting Polling Mode\n")); ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG, ALTERA_PLL_MODE_PLLNG_MD_VAL); - usleep(ALTERA_PLL_WAIT_TIME_US); } /** @@ -182,7 +193,7 @@ void ALTERA_PLL_SetModePolling() { * @param frequency set */ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) { - FILE_LOG(logINFO, ("\tC%d: Setting output frequency\n")); + FILE_LOG(logINFO, ("\tC%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n", clkIndex, value, pllVCOFreqMhz)); // calculate output frequency uint32_t total_div = pllVCOFreqMhz / value; @@ -208,12 +219,9 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) { // write frequency (post-scale output counter C) ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val); - usleep(ALTERA_PLL_WAIT_TIME_US); // reset only PLL - bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask); - usleep(ALTERA_PLL_WAIT_TIME_US); - bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask); + ALTERA_PLL_ResetPLL(); return (pllVCOFreqMhz / (low_count + high_count)); } diff --git a/slsDetectorSoftware/multiSlsDetector/multiSlsDetector.cpp b/slsDetectorSoftware/multiSlsDetector/multiSlsDetector.cpp index 146affe30..925d78ae6 100644 --- a/slsDetectorSoftware/multiSlsDetector/multiSlsDetector.cpp +++ b/slsDetectorSoftware/multiSlsDetector/multiSlsDetector.cpp @@ -1379,7 +1379,7 @@ int multiSlsDetector::setSpeed(speedVariable index, int value, int detPos) { // multi auto r = parallelCall(&slsDetector::setSpeed, index, value); - return (sls::allEqualTo(r, static_cast(OK)) ? OK : FAIL); + return sls::minusOneIfDifferent(r); } int multiSlsDetector::setDynamicRange(int dr, int detPos) { diff --git a/slsDetectorSoftware/slsDetector/slsDetector.cpp b/slsDetectorSoftware/slsDetector/slsDetector.cpp index 3e2892f93..c476bf0a2 100644 --- a/slsDetectorSoftware/slsDetector/slsDetector.cpp +++ b/slsDetectorSoftware/slsDetector/slsDetector.cpp @@ -2720,7 +2720,9 @@ std::string slsDetector::setAdditionalJsonHeader(const std::string &jsonheader) sls::strcpy_safe(args, jsonheader.c_str()); FILE_LOG(logDEBUG1) << "Sending additional json header " << args; - if (thisDetector->receiverOnlineFlag == ONLINE_FLAG) { + if (thisDetector->receiverOnlineFlag != ONLINE_FLAG) { + sls::strcpy_safe(thisDetector->receiver_additionalJsonHeader, jsonheader.c_str()); + } else { auto receiver = sls::ClientSocket(true, thisDetector->receiver_hostname, thisDetector->receiverTCPPort); ret = receiver.sendCommandThenRead(fnum, args, sizeof(args), retvals, sizeof(retvals)); if (ret == FAIL) { diff --git a/slsDetectorSoftware/slsDetector/slsDetectorCommand.cpp b/slsDetectorSoftware/slsDetector/slsDetectorCommand.cpp index 1df99e982..5b917ff1f 100644 --- a/slsDetectorSoftware/slsDetector/slsDetectorCommand.cpp +++ b/slsDetectorSoftware/slsDetector/slsDetectorCommand.cpp @@ -5604,7 +5604,7 @@ std::string slsDetectorCommand::cmdProcessor(int narg, char *args[], int action, return getFrameModeType(frameModeType(myDet->setFrameMode(GET_FRAME_MODE, detPos))); } - else if (cmd == "detectorMode") { + else if (cmd == "detectormode") { if (action == PUT_ACTION) { detectorModeType ival = getDetectorModeType(args[1]); if (ival == GET_DETECTOR_MODE) @@ -5613,7 +5613,7 @@ std::string slsDetectorCommand::cmdProcessor(int narg, char *args[], int action, } return getDetectorModeType(detectorModeType(myDet->setDetectorMode(GET_DETECTOR_MODE, detPos))); } - return std::string("unknown action"); + return std::string("unknown command"); } diff --git a/slsReceiverSoftware/src/slsReceiverImplementation.cpp b/slsReceiverSoftware/src/slsReceiverImplementation.cpp index d4cc1f098..eadfaf74a 100644 --- a/slsReceiverSoftware/src/slsReceiverImplementation.cpp +++ b/slsReceiverSoftware/src/slsReceiverImplementation.cpp @@ -1097,7 +1097,7 @@ void slsReceiverImplementation::stopReceiver() { tot += dataProcessor[i]->GetNumFramesCaught(); uint64_t missingpackets = numberOfFrames*generalData->packetsPerFrame-listener[i]->GetPacketsCaught(); - TLogLevel lev = ((int)missingpackets > 0) ? logINFORED : logINFOGREEN; + TLogLevel lev = (((int64_t)missingpackets) > 0) ? logINFORED : logINFOGREEN; FILE_LOG(lev) << "Summary of Port " << udpPortNum[i] << "\n\tMissing Packets\t\t: " << missingpackets <<