fixed tests for new setbit, clearbit

python/tests/test_bits.py

@@ -1,4 +1,4 @@
-from slsdet.bits import clearbit, clearbit_arr, setbit, setbit_arr
+from slsdet.bits import clearbit, setbit
 from slsdet import RegisterAddress
 import numpy as np
 
@@ -15,20 +15,16 @@ def test_setbit_on_python_int():
     assert r == 7
     assert val == 5
 
-
 def test_setbit_doesnt_change_type():
     word = np.int32(5)
     ret = setbit(0, word)
     assert isinstance(ret, np.int32)
 
-
 def test_clearbit_doesnt_change_type():
     word = np.uint8(5)
     ret = clearbit(0, word)
     assert isinstance(ret, np.uint8)
 
-
-
 def test_setbit_on_array_element():
     arr = np.zeros(10, dtype=np.uint64)
     arr[5] = setbit(0, arr[5])
@@ -38,17 +34,18 @@ def test_setbit_on_array_element():
     assert arr[5] == 19  # 0b10011
     assert arr[6] == 0
 
+def test_setbit_array():
+    test_array = np.zeros(10, dtype=np.int32)
+    test_array[0:3] = setbit(0, test_array[0:3])
+    test_array[3:6] = setbit(1, test_array[3:6])
+    test_array[6:9] = setbit(2, test_array[6:9])
+    test_array[9] = setbit(3, test_array[9])
+    assert all(test_array == np.array((1, 1, 1, 2, 2, 2, 4, 4, 4, 8), dtype=np.int32))
 
-def test_setbit_arr():
-    arr = np.zeros(10, dtype=np.int32)
-    setbit_arr(3, arr[3:9])
-    assert all(arr == np.array((0, 0, 0, 8, 8, 8, 8, 8, 8, 0), dtype=np.int32))
-
-
-def test_clearbit_arr():
-    arr = np.array((5, 5, 5), dtype=np.int8)
-    clearbit_arr(0, arr)
-    assert all(arr == (4, 4, 4))
+def test_clearbit_array():
+    test_array = 5*np.ones(3, dtype=np.int8)
+    test_array[:] = clearbit(0, test_array)
+    assert all(test_array == 4)
 
 def test_RegisterAddress_addition():
     r = RegisterAddress(0x10)

python/tests/test_pattern_generator.py

@@ -1,4 +1,4 @@
-import pytest 
+import pytest
 from slsdet import PatternGenerator
 
 
@@ -24,21 +24,21 @@ def apply_detconf(p):
     en_pll_clk = 15
     cnt_en_2 = 16
     DACINT = 17
-    data_out_slow = 18 #IN
-    COMP2_MON = 19 #IN
+    data_out_slow = 18  # IN
+    COMP2_MON = 19  # IN
     start_read = 20
     dac_store = 21
-    CNT3_MON = 22 #IN
+    CNT3_MON = 22  # IN
     EN_PIX_DIG_MON = 23
     clk_sel = 24
-    BUSY = 25 #IN
-    COMP3_MON = 26 #IN
-    CNT2_MON = 27 #IN
+    BUSY = 25  # IN
+    COMP3_MON = 26  # IN
+    CNT2_MON = 27  # IN
 
-    dbit_ena=62 #FIFO LATCH
-    adc_ena=63  #ADC ENABLE
+    dbit_ena = 62  # FIFO LATCH
+    adc_ena = 63  # ADC ENABLE
 
-    #FPGA input/ouutputs
+    # FPGA input/ouutputs
     p.setoutput(DACMON)
     p.setoutput(cnt_en_3)
     p.setoutput(pulse_counter_en)
@@ -68,27 +68,24 @@ def apply_detconf(p):
     p.setinput(COMP3_MON)
     p.setinput(CNT2_MON)
 
-    #system signals
+    # system signals
     p.setoutput(adc_ena)
     # FIFO LATCH
     p.setoutput(dbit_ena)
-    return p    
-
-
-
+    return p
 
 
 def test_first_two_PW():
     p = PatternGenerator()
 
-    #The pattern is created with a single empty word
+    # The pattern is created with a single empty word
     assert p.pattern.limits[0] == 0
     assert p.pattern.limits[1] == 0
 
     p.SB(8)
     p.PW()
 
-    #When doing the first PW the empty word is overwritten
+    # When doing the first PW the empty word is overwritten
     assert p.pattern.limits[0] == 0
     assert p.pattern.limits[1] == 0
     assert p.pattern.word[0] == 256
@@ -96,12 +93,13 @@ def test_first_two_PW():
     p.SB(9)
     p.PW()
 
-    #When doing the second PW we add a new word
+    # When doing the second PW we add a new word
     assert p.pattern.limits[0] == 0
     assert p.pattern.limits[1] == 1
     assert p.pattern.word[0] == 256
     assert p.pattern.word[1] == 768
 
+
 def test_simple_pattern():
     """
     Using enable pll pattern for MH02
@@ -111,7 +109,7 @@ def test_simple_pattern():
     p = apply_detconf(p)
     p.SB(en_pll_clk)
     p.PW()
-    p.PW() 
+    p.PW()
 
     lines = str(p).split("\n")
 
@@ -149,4 +147,4 @@ def test_simple_pattern():
     assert len(lines) == len(enable_pll_pattern)
 
     for i, line in enumerate(lines):
-        assert line == enable_pll_pattern[i]
+        assert line == enable_pll_pattern[i]