mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 10:07:59 +02:00
start with unification of pattern machinery for xctb, ctb, mythen
This commit is contained in:
@ -119,7 +119,7 @@
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#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
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/* API Version RO register */
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#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
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#define API_VERSION_REG (0x0B << MEM_MAP_SHIFT)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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@ -128,24 +128,24 @@
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/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
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* CONTROL_CRST. TODO */
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#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
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#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
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#define TIME_FROM_START_LSB_REG (0x97 << MEM_MAP_SHIFT)
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#define TIME_FROM_START_MSB_REG (0x98 << MEM_MAP_SHIFT)
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/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
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#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
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#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
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#define DELAY_LEFT_LSB_REG (0x8D << MEM_MAP_SHIFT)
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#define DELAY_LEFT_MSB_REG (0x8E << MEM_MAP_SHIFT)
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/* Triggers Left 64 bit RO register TODO */
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#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
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#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
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#define CYCLES_LEFT_LSB_REG (0x8F << MEM_MAP_SHIFT)
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#define CYCLES_LEFT_MSB_REG (0x90 << MEM_MAP_SHIFT)
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/* Frames Left 64 bit RO register TODO */
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#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
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#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
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#define FRAMES_LEFT_LSB_REG (0x91 << MEM_MAP_SHIFT)
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#define FRAMES_LEFT_MSB_REG (0x92 << MEM_MAP_SHIFT)
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/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
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#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
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#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
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#define PERIOD_LEFT_LSB_REG (0x93 << MEM_MAP_SHIFT)
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#define PERIOD_LEFT_MSB_REG (0x94 << MEM_MAP_SHIFT)
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/* Exposure Time Left 64 bit RO register */
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// #define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
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@ -160,34 +160,34 @@
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//// Not used in FW
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/* Data In 64 bit RO register TODO */
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#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
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#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
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#define DATA_IN_LSB_REG (0x10 << MEM_MAP_SHIFT)
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#define DATA_IN_MSB_REG (0x11 << MEM_MAP_SHIFT)
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/* Pattern Out 64 bit RO register */
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#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
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#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
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#define PATTERN_OUT_LSB_REG (0x80 << MEM_MAP_SHIFT)
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#define PATTERN_OUT_MSB_REG (0x81 << MEM_MAP_SHIFT)
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/* Frame number of next acquisition register (64 bit register) */
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#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x22 << MEM_MAP_SHIFT)
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#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x23 << MEM_MAP_SHIFT)
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#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x12 << MEM_MAP_SHIFT)
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#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x13 << MEM_MAP_SHIFT)
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/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
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#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
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#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
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#define FRAMES_FROM_START_PG_LSB_REG (0x99 << MEM_MAP_SHIFT)
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#define FRAMES_FROM_START_PG_MSB_REG (0x9A << MEM_MAP_SHIFT)
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/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
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* start until reset) TODO */
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#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
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#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
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#define START_FRAME_TIME_LSB_REG (0x9B << MEM_MAP_SHIFT)
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#define START_FRAME_TIME_MSB_REG (0x9C << MEM_MAP_SHIFT)
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/* Power Status RO register */
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#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
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#define POWER_STATUS_REG (0x18 << MEM_MAP_SHIFT)
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#define POWER_STATUS_ALRT_OFST (27)
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#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
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/* FIFO Transceiver In Status RO register */
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#define FIFO_TIN_STATUS_REG (0x30 << MEM_MAP_SHIFT)
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#define FIFO_TIN_STATUS_REG (0x1A << MEM_MAP_SHIFT)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST (4)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_1_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST (5)
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@ -199,19 +199,19 @@
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#define FIFO_TIN_STATUS_FIFO_EMPTY_ALL_MSK (0x0000000F << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
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/* FIFO Transceiver Fill level RO register */
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#define FIFO_TIN_FILL_REG (0x45 << MEM_MAP_SHIFT)
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#define FIFO_TIN_FILL_REG (0x25 << MEM_MAP_SHIFT)
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#define FIFO_TIN_FILL_FIFO_1_OFST (0)
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#define FIFO_TIN_FILL_FIFO_1_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__1_OFST)
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#define FIFO_TIN_FILL_FIFO_2_OFST (16)
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#define FIFO_TIN_FILL_FIFO_2_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__2_OFST)
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/* FIFO ADC Fill level RO register */
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#define FIFO_ADC_FILL_REG (0x46 << MEM_MAP_SHIFT)
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#define FIFO_ADC_FILL_REG (0x26 << MEM_MAP_SHIFT)
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#define FIFO_ADC_FILL_FIFO_OFST (0)
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#define FIFO_ADC_FILL_FIFO_MSK (0x00003FFF << FIFO_ADC_FILL_FIFO_OFST)
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/* Enable continuos readout register */
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#define CONTINUOUS_RO_ENABLE_REG (0x47 << MEM_MAP_SHIFT)
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#define CONTINUOUS_RO_ENABLE_REG (0x27 << MEM_MAP_SHIFT)
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#define CONTINUOUS_RO_ADC_ENABLE_OFST (0)
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#define CONTINUOUS_RO_TIN_ENABLE_OFST (1)
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#define CONTINUOUS_RO_DBIT_ENABLE_OFST (2)
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@ -224,15 +224,15 @@
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#define DBIT_INJECT_COUNTER_CLKDIV_MSK (0x000000FF << DBIT_INJECT_COUNTER_CLKDIV_OFST)
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/* 64-bit FPGA chip ID. Unique for every device. read-only */
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#define FPGA_chipID_0_REG (0x48 << MEM_MAP_SHIFT)
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#define FPGA_chipID_1_REG (0x49 << MEM_MAP_SHIFT)
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#define FPGA_chipID_0_REG (0x28 << MEM_MAP_SHIFT)
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#define FPGA_chipID_1_REG (0x29 << MEM_MAP_SHIFT)
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/* FIFO Transceiver In 64 bit RO register */
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#define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT)
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#define FIFO_TIN_MSB_REG (0x32 << MEM_MAP_SHIFT)
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#define FIFO_TIN_LSB_REG (0x1B << MEM_MAP_SHIFT)
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#define FIFO_TIN_MSB_REG (0x1C << MEM_MAP_SHIFT)
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/* FIFO Digital In Status RO register */
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#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
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#define FIFO_DIN_STATUS_REG (0x1D << MEM_MAP_SHIFT)
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#define FIFO_DIN_STATUS_FIFO_FILL_OFST (0)
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#define FIFO_DIN_STATUS_FIFO_FILL_MSK (0x00003FFF)
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#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
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@ -241,11 +241,11 @@
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#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
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/* FIFO Digital In 64 bit RO register */
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#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
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#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
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#define FIFO_DIN_LSB_REG (0x1E << MEM_MAP_SHIFT)
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#define FIFO_DIN_MSB_REG (0x1F << MEM_MAP_SHIFT)
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/* SPI (Serial Peripheral Interface) DAC, HV RW register */
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#define SPI_REG (0x40 << MEM_MAP_SHIFT)
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#define SPI_REG (0x20 << MEM_MAP_SHIFT)
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#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
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#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
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@ -261,7 +261,7 @@
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#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
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/* ADC SPI (Serial Peripheral Interface) RW register */
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#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
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#define ADC_SPI_REG (0x21 << MEM_MAP_SHIFT)
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#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
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#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
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@ -271,7 +271,7 @@
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#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
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/* ADC Offset RW register */
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#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
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#define ADC_OFFSET_REG (0x22 << MEM_MAP_SHIFT)
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#define ADC_OFFSET_ADC_PPLN_OFST (0)
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#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
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@ -279,7 +279,7 @@
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#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
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/* ADC Port Invert RW register */
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#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
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#define ADC_PORT_INVERT_REG (0x23 << MEM_MAP_SHIFT)
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#define ADC_PORT_INVERT_0_INPT_OFST (0)
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#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
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@ -291,7 +291,7 @@
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#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
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/* Dummy RW register */
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#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
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#define DUMMY_REG (0x24 << MEM_MAP_SHIFT)
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#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
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#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
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@ -305,7 +305,7 @@
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#define DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST)
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/* Configuration RW register */
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#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
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#define CONFIG_REG (0x2D << MEM_MAP_SHIFT)
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#define CONFIG_LED_DSBL_OFST (0)
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#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
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@ -320,7 +320,7 @@
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#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
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/* External Signal RW register */
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#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
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#define EXT_SIGNAL_REG (0x2E << MEM_MAP_SHIFT)
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#define EXT_SIGNAL_OFST (0)
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#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
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@ -328,7 +328,7 @@
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#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
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/* Control RW register */
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#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
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#define CONTROL_REG (0x2F << MEM_MAP_SHIFT)
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#define CONTROL_STRT_ACQSTN_OFST (0)
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#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
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@ -368,10 +368,10 @@
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#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
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/* Reconfiguratble PLL Paramater RW register */
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#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
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#define PLL_PARAM_REG (0x30 << MEM_MAP_SHIFT)
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/* Reconfiguratble PLL Control RW regiser */
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#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
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#define PLL_CNTRL_REG (0x31 << MEM_MAP_SHIFT)
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#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
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#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
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@ -384,7 +384,7 @@
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#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
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/* Pattern Control RW register */
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#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
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#define PATTERN_CNTRL_REG (0x88 << MEM_MAP_SHIFT)
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#define PATTERN_CNTRL_WR_OFST (0)
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#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
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@ -394,7 +394,7 @@
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#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
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/* Pattern Limit RW regiser */
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#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
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#define PATTERN_LIMIT_REG (0x89 << MEM_MAP_SHIFT)
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
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@ -402,7 +402,7 @@
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#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
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/* Pattern Loop 0 Address RW regiser */
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#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_0_ADDR_REG (0xA0 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK \
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@ -411,10 +411,10 @@
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
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/* Pattern Loop 0 Iteration RW regiser */
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#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_0_ITERATION_REG (0xA1 << MEM_MAP_SHIFT)
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/* Pattern Loop 1 Address RW regiser */
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#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_1_ADDR_REG (0xA5 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK \
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@ -423,10 +423,10 @@
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
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/* Pattern Loop 1 Iteration RW regiser */
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#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_1_ITERATION_REG (0xA6 << MEM_MAP_SHIFT)
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/* Pattern Loop 2 Address RW regiser */
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#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_2_ADDR_REG (0xAA << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK \
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@ -435,29 +435,29 @@
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
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/* Pattern Loop 2 Iteration RW regiser */
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#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_2_ITERATION_REG (0xAB << MEM_MAP_SHIFT)
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/* Pattern Wait 0 RW regiser */
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#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_0_ADDR_REG (0xA2 << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_0_ADDR_OFST (0)
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#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
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// FIXME: is mask 3FF
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/* Pattern Wait 1 RW regiser */
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#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_1_ADDR_REG (0xA7 << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_1_ADDR_OFST (0)
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#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
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/* Pattern Wait 2 RW regiser */
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#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_2_ADDR_REG (0xAC << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_2_ADDR_OFST (0)
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#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
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/* Samples RW register */
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#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
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#define SAMPLES_REG (0x32 << MEM_MAP_SHIFT)
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#define SAMPLES_DIGITAL_OFST (0)
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#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
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@ -465,7 +465,7 @@
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#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
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/** Power RW register */
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#define POWER_REG (0x5E << MEM_MAP_SHIFT)
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#define POWER_REG (0x33 << MEM_MAP_SHIFT)
|
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#define POWER_ENBL_VLTG_RGLTR_OFST (16)
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#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
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@ -473,25 +473,25 @@
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#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
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||||
|
||||
/* Number of samples from transceiver RW register */
|
||||
#define SAMPLES_TRANSCEIVER_REG (0x5F << MEM_MAP_SHIFT)
|
||||
#define SAMPLES_TRANSCEIVER_REG (0x34 << MEM_MAP_SHIFT)
|
||||
#define SAMPLES_TRANSCEIVER_OFST (0)
|
||||
#define SAMPLES_TRANSCEIVER_MSK (0x0000FFFF << SAMPLES_TRANSCEIVER_OFST)
|
||||
|
||||
/* Delay 64 bit RW register. t = DLY x 50 ns. */
|
||||
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
|
||||
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
|
||||
#define DELAY_LSB_REG (0x8D << MEM_MAP_SHIFT)
|
||||
#define DELAY_MSB_REG (0x8E << MEM_MAP_SHIFT)
|
||||
|
||||
/* Triggers 64 bit RW register */
|
||||
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
|
||||
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
|
||||
#define CYCLES_LSB_REG (0x8F << MEM_MAP_SHIFT)
|
||||
#define CYCLES_MSB_REG (0x90 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Frames 64 bit RW register */
|
||||
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_LSB_REG (0x91 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_MSB_REG (0x92 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Period 64 bit RW register */
|
||||
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
|
||||
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
|
||||
#define PERIOD_LSB_REG (0x93 << MEM_MAP_SHIFT)
|
||||
#define PERIOD_MSB_REG (0x94 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Period 64 bit RW register */
|
||||
// #define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
|
||||
@ -506,33 +506,27 @@
|
||||
|
||||
/* Pattern IO Control 64 bit RW regiser
|
||||
* Each bit configured as output(1)/ input(0) */
|
||||
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern IO Clock Control 64 bit RW regiser
|
||||
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
|
||||
* When bit n disabled (0), Dio[n] driven by its pattern output */
|
||||
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CNTRL_LSB_REG (0x8A << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CNTRL_MSB_REG (0x8B << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern In 64 bit RW register */
|
||||
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IN_LSB_REG (0x82 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IN_MSB_REG (0x83 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_0_LSB_REG (0xA3 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_0_MSB_REG (0xA4 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_1_LSB_REG (0xA8 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_1_MSB_REG (0xA9 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0xAD << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0xAE << MEM_MAP_SHIFT)
|
||||
|
||||
/* Readout enable RW register */
|
||||
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
|
||||
#define READOUT_10G_ENABLE_REG (0x3C << MEM_MAP_SHIFT)
|
||||
|
||||
#define READOUT_10G_ENABLE_ANLG_OFST (0)
|
||||
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
|
||||
@ -543,7 +537,7 @@
|
||||
(0x0000000F << READOUT_10G_ENABLE_TRNSCVR_OFST)
|
||||
|
||||
/* Digital Bit External Trigger RW register */
|
||||
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
|
||||
#define DBIT_EXT_TRG_REG (0x3E << MEM_MAP_SHIFT)
|
||||
|
||||
#define DBIT_EXT_TRG_SRC_OFST (0)
|
||||
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
|
||||
@ -551,7 +545,7 @@
|
||||
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
|
||||
|
||||
/* Pin Delay 0 RW register */
|
||||
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
|
||||
#define OUTPUT_DELAY_0_REG (0x3F << MEM_MAP_SHIFT)
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
|
||||
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
|
||||
@ -567,18 +561,18 @@
|
||||
|
||||
/* Pin Delay 1 RW register
|
||||
* Each bit configured as enable for dynamic output delay configuration */
|
||||
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
|
||||
#define PIN_DELAY_1_REG (0x40 << MEM_MAP_SHIFT)
|
||||
|
||||
/** Pattern Mask 64 bit RW regiser */
|
||||
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_MASK_LSB_REG (0x84 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_MASK_MSB_REG (0x85 << MEM_MAP_SHIFT)
|
||||
|
||||
/** Pattern Set 64 bit RW regiser */
|
||||
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_SET_LSB_REG (0x86 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_SET_MSB_REG (0x87 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Loop 3 Address RW regiser */
|
||||
#define PATTERN_LOOP_3_ADDR_REG (0x84 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_3_ADDR_REG (0xAF << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
|
||||
@ -587,10 +581,10 @@
|
||||
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_3_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 3 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_3_ITERATION_REG (0x85 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_3_ITERATION_REG (0xB0 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Loop 4 Address RW regiser */
|
||||
#define PATTERN_LOOP_4_ADDR_REG (0x86 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_4_ADDR_REG (0xB4 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
|
||||
@ -599,10 +593,10 @@
|
||||
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_4_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 4 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_4_ITERATION_REG (0x87 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_4_ITERATION_REG (0xB5 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Loop 5 Address RW regiser */
|
||||
#define PATTERN_LOOP_5_ADDR_REG (0x88 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_5_ADDR_REG (0xB9 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
|
||||
@ -611,43 +605,43 @@
|
||||
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_5_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 5 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_5_ITERATION_REG (0x89 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_5_ITERATION_REG (0xBA << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait 3 RW regiser */
|
||||
#define PATTERN_WAIT_3_ADDR_REG (0x8A << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_3_ADDR_REG (0xB1 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_3_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_3_ADDR_MSK (0x00001FFF << PATTERN_WAIT_3_ADDR_OFST)
|
||||
|
||||
/* Pattern Wait 4 RW regiser */
|
||||
#define PATTERN_WAIT_4_ADDR_REG (0x8B << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_4_ADDR_REG (0xB6 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_4_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_4_ADDR_MSK (0x00001FFF << PATTERN_WAIT_4_ADDR_OFST)
|
||||
|
||||
/* Pattern Wait 5 RW regiser */
|
||||
#define PATTERN_WAIT_5_ADDR_REG (0x8C << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_5_ADDR_REG (0xBB << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_5_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_5_ADDR_MSK (0x00001FFF << PATTERN_WAIT_5_ADDR_OFST)
|
||||
|
||||
/* Pattern Wait Timer 3 64 bit RW register. t = PWT1 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_3_LSB_REG (0x8D << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_3_MSB_REG (0x8E << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB2 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB3 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 4 64 bit RW register. t = PWT1 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_4_LSB_REG (0x8F << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_4_MSB_REG (0x90 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB7 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB8 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 5 64 bit RW register. t = PWT1 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_5_LSB_REG (0x91 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_5_MSB_REG (0x92 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_5_LSB_REG (0xBC << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_5_MSB_REG (0xBD << MEM_MAP_SHIFT)
|
||||
|
||||
/* Slow ADC SPI Value RO register */
|
||||
#define ADC_SLOW_DATA_REG (0x93 << MEM_MAP_SHIFT)
|
||||
#define ADC_SLOW_DATA_REG (0x41 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Slow ADC SPI Value Config register */
|
||||
#define ADC_SLOW_CFG_REG (0x94 << MEM_MAP_SHIFT)
|
||||
#define ADC_SLOW_CFG_REG (0x42 << MEM_MAP_SHIFT)
|
||||
/** Read back CFG Register */
|
||||
#define ADC_SLOW_CFG_RB_OFST (2)
|
||||
#define ADC_SLOW_CFG_RB_MSK (0x00000001 << ADC_SLOW_CFG_RB_OFST)
|
||||
@ -726,7 +720,7 @@
|
||||
((0x1 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
|
||||
|
||||
/* Slow ADC SPI Value Control register */
|
||||
#define ADC_SLOW_CTRL_REG (0x95 << MEM_MAP_SHIFT)
|
||||
#define ADC_SLOW_CTRL_REG (0x43 << MEM_MAP_SHIFT)
|
||||
|
||||
#define ADC_SLOW_CTRL_STRT_OFST (0)
|
||||
#define ADC_SLOW_CTRL_STRT_MSK (0x00000001 << ADC_SLOW_CTRL_STRT_OFST)
|
||||
|
||||
@ -2,6 +2,8 @@
|
||||
// Copyright (C) 2021 Contributors to the SLS Detector Package
|
||||
#pragma once
|
||||
|
||||
#define PATTERN_RAM_BASE_ADDR (0x0000)
|
||||
|
||||
#define CTRL_REG (0x8000)
|
||||
|
||||
#define POWER_VIO_OFST (0)
|
||||
@ -116,8 +118,7 @@
|
||||
#define RO_MODE_X_OFST (15)
|
||||
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
|
||||
#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
|
||||
#define COUNT_FRAMES_FROM_UPDATE_MSK \
|
||||
(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
|
||||
#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
|
||||
#define START_STREAMING_P_OFST (17)
|
||||
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
|
||||
#define STREAM_BUFFER_CLEAR_OFST (18)
|
||||
@ -181,16 +182,43 @@
|
||||
#define COORDZ_OFST (0)
|
||||
#define COORDZ_MSK (0x0000ffff << COORDZ_OFST)
|
||||
|
||||
#define FLOW_STATUS_REG (0xB000)
|
||||
#define PATTERN_OUT_LSB_REG (0xB000)
|
||||
|
||||
#define RSM_BUSY_OFST (0)
|
||||
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
|
||||
#define RSM_TRG_WAIT_OFST (3)
|
||||
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
|
||||
#define CSM_BUSY_OFST (17)
|
||||
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
|
||||
#define PATTERN_OUT_MSB_REG (0xB004)
|
||||
|
||||
#define FLOW_CONTROL_REG (0xB004)
|
||||
#define PATTERN_IN_LSB_REG (0xB008)
|
||||
|
||||
#define PATTERN_IN_MSB_REG (0xB00C)
|
||||
|
||||
#define PATTERN_MASK_LSB_REG (0xB010)
|
||||
|
||||
#define PATTERN_MASK_MSB_REG (0xB014)
|
||||
|
||||
#define PATTERN_SET_LSB_REG (0xB018)
|
||||
|
||||
#define PATTERN_SET_MSB_REG (0xB01C)
|
||||
|
||||
#define PATTERN_CNTRL_REG (0xB020)
|
||||
|
||||
#define PATTERN_CNTRL_WR_OFST (0)
|
||||
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
|
||||
#define PATTERN_CNTRL_RD_OFST (1)
|
||||
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
|
||||
#define PATTERN_CNTRL_ADDR_OFST (16)
|
||||
#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
|
||||
|
||||
#define PATTERN_LIMIT_REG (0xB024)
|
||||
|
||||
#define PATTERN_LIMIT_STRT_OFST (0)
|
||||
#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST)
|
||||
#define PATTERN_LIMIT_STP_OFST (16)
|
||||
#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
|
||||
|
||||
#define PATTERN_IO_CNTRL_LSB_REG (0xB028)
|
||||
|
||||
#define PATTERN_IO_CNTRL_MSB_REG (0xB02C)
|
||||
|
||||
#define FLOW_CONTROL_REG (0xB030)
|
||||
|
||||
#define START_F_OFST (0)
|
||||
#define START_F_MSK (0x00000001 << START_F_OFST)
|
||||
@ -202,200 +230,84 @@
|
||||
#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
|
||||
#define TRIGGER_ENABLE_OFST (4)
|
||||
#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
|
||||
#define RSM_BUSY_OFST (5)
|
||||
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
|
||||
#define RSM_TRG_WAIT_OFST (6)
|
||||
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
|
||||
#define CSM_BUSY_OFST (7)
|
||||
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
|
||||
|
||||
#define TIME_FROM_START_OUT_REG_1 (0xB008)
|
||||
#define DELAY_IN_REG_1 (0xB034)
|
||||
|
||||
#define TIME_FROM_START_OUT_REG_2 (0xB00C)
|
||||
#define DELAY_IN_REG_2 (0xB038)
|
||||
|
||||
#define FRAMES_FROM_START_OUT_REG_1 (0xB010)
|
||||
#define CYCLES_IN_REG_1 (0xB03C)
|
||||
|
||||
#define FRAMES_FROM_START_OUT_REG_2 (0xB014)
|
||||
#define CYCLES_IN_REG_2 (0xB040)
|
||||
|
||||
#define FRAME_TIME_OUT_REG_1 (0xB018)
|
||||
#define FRAMES_IN_REG_1 (0xB044)
|
||||
|
||||
#define FRAME_TIME_OUT_REG_2 (0xB01C)
|
||||
#define FRAMES_IN_REG_2 (0xB048)
|
||||
|
||||
#define DELAY_OUT_REG_1 (0xB020)
|
||||
#define PERIOD_IN_REG_1 (0xB04C)
|
||||
|
||||
#define DELAY_OUT_REG_2 (0xB024)
|
||||
#define PERIOD_IN_REG_2 (0xB050)
|
||||
|
||||
#define CYCLES_OUT_REG_1 (0xB028)
|
||||
#define DELAY_OUT_REG_1 (0xB054)
|
||||
|
||||
#define CYCLES_OUT_REG_2 (0xB02C)
|
||||
#define DELAY_OUT_REG_2 (0xB058)
|
||||
|
||||
#define FRAMES_OUT_REG_1 (0xB030)
|
||||
#define CYCLES_OUT_REG_1 (0xB05C)
|
||||
|
||||
#define FRAMES_OUT_REG_2 (0xB034)
|
||||
#define CYCLES_OUT_REG_2 (0xB060)
|
||||
|
||||
#define PERIOD_OUT_REG_1 (0xB038)
|
||||
#define FRAMES_OUT_REG_1 (0xB064)
|
||||
|
||||
#define PERIOD_OUT_REG_2 (0xB03C)
|
||||
#define FRAMES_OUT_REG_2 (0xB068)
|
||||
|
||||
#define DELAY_IN_REG_1 (0xB040)
|
||||
#define PERIOD_OUT_REG_1 (0xB06C)
|
||||
|
||||
#define DELAY_IN_REG_2 (0xB044)
|
||||
#define PERIOD_OUT_REG_2 (0xB070)
|
||||
|
||||
#define CYCLES_IN_REG_1 (0xB048)
|
||||
#define PATTERN_TEST_REG (0xB074)
|
||||
|
||||
#define CYCLES_IN_REG_2 (0xB04C)
|
||||
#define PATTERN_FIRMWARE_REG (0xB078)
|
||||
|
||||
#define FRAMES_IN_REG_1 (0xB050)
|
||||
#define PATTERN_WIDTH_OFST (0)
|
||||
#define PATTERN_WIDTH_MSK (0x000000ff << PATTERN_WIDTH_OFST)
|
||||
#define PATTERN_ADDR_WIDTH_OFST (8)
|
||||
#define PATTERN_ADDR_WIDTH_MSK (0x000000ff << PATTERN_ADDR_WIDTH_OFST)
|
||||
#define PATTERN_NLOOPS_NWAITS_OFST (16)
|
||||
#define PATTERN_NLOOPS_NWAITS_MSK (0x000000ff << PATTERN_NLOOPS_NWAITS_OFST)
|
||||
#define DIRECT_PATTERN_RAM_OFST (24)
|
||||
#define DIRECT_PATTERN_RAM_MSK (0x00000001 << DIRECT_PATTERN_RAM_OFST)
|
||||
|
||||
#define FRAMES_IN_REG_2 (0xB054)
|
||||
#define TIME_FROM_START_OUT_REG_1 (0xB07C)
|
||||
|
||||
#define PERIOD_IN_REG_1 (0xB058)
|
||||
#define TIME_FROM_START_OUT_REG_2 (0xB080)
|
||||
|
||||
#define PERIOD_IN_REG_2 (0xB05C)
|
||||
#define FRAMES_FROM_START_OUT_REG_1 (0xB084)
|
||||
|
||||
#define PATTERN_OUT_LSB_REG (0xB100)
|
||||
#define FRAMES_FROM_START_OUT_REG_2 (0xB088)
|
||||
|
||||
#define PATTERN_OUT_MSB_REG (0xB104)
|
||||
#define FRAME_TIME_OUT_REG_1 (0xB08C)
|
||||
|
||||
#define PATTERN_IN_LSB_REG (0xB108)
|
||||
#define FRAME_TIME_OUT_REG_2 (0xB090)
|
||||
|
||||
#define PATTERN_IN_MSB_REG (0xB10C)
|
||||
#define PATTERN_LOOPDEF_START_REG (0xB100)
|
||||
|
||||
#define PATTERN_MASK_LSB_REG (0xB110)
|
||||
#define PATTERN_LOOPDEF_LOOP_ADDR_OFST (0)
|
||||
#define PATTERN_LOOPDEF_LOOP_ADDR_MSK (0x00000001 << PATTERN_LOOPDEF_LOOP_ADDR_OFST)
|
||||
#define PATTERN_LOOPDEF_LOOP_ITERATION_OFST (1)
|
||||
#define PATTERN_LOOPDEF_LOOP_ITERATION_MSK (0x00000001 << PATTERN_LOOPDEF_LOOP_ITERATION_OFST)
|
||||
#define PATTERN_LOOPDEF_WAIT_ADDR_OFST (2)
|
||||
#define PATTERN_LOOPDEF_WAIT_ADDR_MSK (0x00000001 << PATTERN_LOOPDEF_WAIT_ADDR_OFST)
|
||||
#define PATTERN_LOOPDEF_WAIT_TIME_LSB_OFST (3)
|
||||
#define PATTERN_LOOPDEF_WAIT_TIME_LSB_MSK (0x00000001 << PATTERN_LOOPDEF_WAIT_TIME_LSB_OFST)
|
||||
#define PATTERN_LOOPDEF_WAIT_TIME_MSB_OFST (4)
|
||||
#define PATTERN_LOOPDEF_WAIT_TIME_MSB_MSK (0x00000001 << PATTERN_LOOPDEF_WAIT_TIME_MSB_OFST)
|
||||
|
||||
#define PATTERN_MASK_MSB_REG (0xB114)
|
||||
|
||||
#define PATTERN_SET_LSB_REG (0xB118)
|
||||
|
||||
#define PATTERN_SET_MSB_REG (0xB11C)
|
||||
|
||||
#define PATTERN_CNTRL_REG (0xB120)
|
||||
|
||||
#define PATTERN_CNTRL_WR_OFST (0)
|
||||
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
|
||||
#define PATTERN_CNTRL_RD_OFST (1)
|
||||
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
|
||||
#define PATTERN_CNTRL_ADDR_OFST (16)
|
||||
#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
|
||||
|
||||
#define PATTERN_LIMIT_REG (0xB124)
|
||||
|
||||
#define PATTERN_LIMIT_STRT_OFST (0)
|
||||
#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST)
|
||||
#define PATTERN_LIMIT_STP_OFST (16)
|
||||
#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_0_ADDR_REG (0xB128)
|
||||
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_0_ITERATION_REG (0xB12C)
|
||||
|
||||
#define PATTERN_WAIT_0_ADDR_REG (0xB130)
|
||||
|
||||
#define PATTERN_WAIT_0_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB134)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB138)
|
||||
|
||||
#define PATTERN_LOOP_1_ADDR_REG (0xB13C)
|
||||
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_1_ITERATION_REG (0xB140)
|
||||
|
||||
#define PATTERN_WAIT_1_ADDR_REG (0xB144)
|
||||
|
||||
#define PATTERN_WAIT_1_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB148)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB14C)
|
||||
|
||||
#define PATTERN_LOOP_2_ADDR_REG (0xB150)
|
||||
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_2_ITERATION_REG (0xB154)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_REG (0xB158)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB15C)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB160)
|
||||
|
||||
#define PATTERN_LOOP_3_ADDR_REG (0xB164)
|
||||
|
||||
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_3_ITERATION_REG (0xB168)
|
||||
|
||||
#define PATTERN_WAIT_3_ADDR_REG (0xB16C)
|
||||
|
||||
#define PATTERN_WAIT_3_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB170)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB174)
|
||||
|
||||
#define PATTERN_LOOP_4_ADDR_REG (0xB178)
|
||||
|
||||
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_4_ITERATION_REG (0xB17C)
|
||||
|
||||
#define PATTERN_WAIT_4_ADDR_REG (0xB180)
|
||||
|
||||
#define PATTERN_WAIT_4_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB184)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB188)
|
||||
|
||||
#define PATTERN_LOOP_5_ADDR_REG (0xB18C)
|
||||
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_5_ITERATION_REG (0xB190)
|
||||
|
||||
#define PATTERN_WAIT_5_ADDR_REG (0xB194)
|
||||
|
||||
#define PATTERN_WAIT_5_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB198)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB19C)
|
||||
|
||||
#define PINIOCTRLREG (0xB1A0)
|
||||
|
||||
#define DBITFIFOCTRLREG (0xB1A4)
|
||||
#define DBITFIFOCTRLREG (0xC000)
|
||||
|
||||
#define DBITRD_OFST (0)
|
||||
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
|
||||
@ -410,15 +322,15 @@
|
||||
#define DBITOVERFLOW_OFST (5)
|
||||
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
|
||||
|
||||
#define DBITFIFODATAREG1 (0xB1A8)
|
||||
#define DBITFIFODATAREG1 (0xC004)
|
||||
|
||||
#define DBITFIFODATAREG2 (0xB1AC)
|
||||
#define DBITFIFODATAREG2 (0xC008)
|
||||
|
||||
#define MATTERHORNSPIREG1 (0xB1B0)
|
||||
#define MATTERHORNSPIREG1 (0xC00C)
|
||||
|
||||
#define MATTERHORNSPIREG2 (0xB1B4)
|
||||
#define MATTERHORNSPIREG2 (0xC010)
|
||||
|
||||
#define MATTERHORNSPICTRL (0xB1B8)
|
||||
#define MATTERHORNSPICTRL (0xC014)
|
||||
|
||||
#define CONFIGSTART_P_OFST (0)
|
||||
#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
|
||||
@ -431,19 +343,19 @@
|
||||
#define READOUTFROMASIC_OFST (4)
|
||||
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
|
||||
|
||||
#define TRANSCEIVERRXCTRL0REG1 (0xB800)
|
||||
#define TRANSCEIVERRXCTRL0REG1 (0xC100)
|
||||
|
||||
#define TRANSCEIVERRXCTRL0REG2 (0xB804)
|
||||
#define TRANSCEIVERRXCTRL0REG2 (0xC104)
|
||||
|
||||
#define TRANSCEIVERRXCTRL1REG1 (0xB808)
|
||||
#define TRANSCEIVERRXCTRL1REG1 (0xC108)
|
||||
|
||||
#define TRANSCEIVERRXCTRL1REG2 (0xB80C)
|
||||
#define TRANSCEIVERRXCTRL1REG2 (0xC10C)
|
||||
|
||||
#define TRANSCEIVERRXCTRL2REG (0xB810)
|
||||
#define TRANSCEIVERRXCTRL2REG (0xC110)
|
||||
|
||||
#define TRANSCEIVERRXCTRL3REG (0xB814)
|
||||
#define TRANSCEIVERRXCTRL3REG (0xC114)
|
||||
|
||||
#define TRANSCEIVERSTATUS (0xB818)
|
||||
#define TRANSCEIVERSTATUS (0xC118)
|
||||
|
||||
#define LINKDOWNLATCHEDOUT_OFST (0)
|
||||
#define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
|
||||
@ -470,12 +382,12 @@
|
||||
#define GTTPOWERGOOD_OFST (26)
|
||||
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
|
||||
|
||||
#define TRANSCEIVERSTATUS2 (0xB81C)
|
||||
#define TRANSCEIVERSTATUS2 (0xC11C)
|
||||
|
||||
#define RXLOCKED_OFST (0)
|
||||
#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
|
||||
|
||||
#define TRANSCEIVERCONTROL (0xB820)
|
||||
#define TRANSCEIVERCONTROL (0xC120)
|
||||
|
||||
#define GTWIZRESETALL_OFST (0)
|
||||
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
|
||||
@ -494,50 +406,169 @@
|
||||
#define RXMSBLSBINVERT_OFST (13)
|
||||
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG0 (0xB824)
|
||||
#define TRANSCEIVERERRCNT_REG0 (0xC124)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG1 (0xB828)
|
||||
#define TRANSCEIVERERRCNT_REG1 (0xC128)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG2 (0xB82C)
|
||||
#define TRANSCEIVERERRCNT_REG2 (0xC12C)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG3 (0xB830)
|
||||
#define TRANSCEIVERERRCNT_REG3 (0xC130)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG0 (0xB834)
|
||||
#define TRANSCEIVERALIGNCNT_REG0 (0xC134)
|
||||
|
||||
#define RXALIGNCNTCH0_OFST (0)
|
||||
#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG1 (0xB838)
|
||||
#define TRANSCEIVERALIGNCNT_REG1 (0xC138)
|
||||
|
||||
#define RXALIGNCNTCH1_OFST (0)
|
||||
#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG2 (0xB83C)
|
||||
#define TRANSCEIVERALIGNCNT_REG2 (0xC13C)
|
||||
|
||||
#define RXALIGNCNTCH2_OFST (0)
|
||||
#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG3 (0xB840)
|
||||
#define TRANSCEIVERALIGNCNT_REG3 (0xC140)
|
||||
|
||||
#define RXALIGNCNTCH3_OFST (0)
|
||||
#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG0 (0xB844)
|
||||
#define TRANSCEIVERLASTWORD_REG0 (0xC144)
|
||||
|
||||
#define RXDATACH0_OFST (0)
|
||||
#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG1 (0xB848)
|
||||
#define TRANSCEIVERLASTWORD_REG1 (0xC148)
|
||||
|
||||
#define RXDATACH1_OFST (0)
|
||||
#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG2 (0xB84C)
|
||||
#define TRANSCEIVERLASTWORD_REG2 (0xC14C)
|
||||
|
||||
#define RXDATACH2_OFST (0)
|
||||
#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG3 (0xB850)
|
||||
#define TRANSCEIVERLASTWORD_REG3 (0xC150)
|
||||
|
||||
#define RXDATACH3_OFST (0)
|
||||
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
|
||||
|
||||
|
||||
|
||||
|
||||
// ----------------------------------------------------
|
||||
// TODO: remove these:
|
||||
|
||||
|
||||
//-----------------------------------
|
||||
#define PINIOCTRLREG (0xB028)
|
||||
|
||||
#define PATTERN_LOOP_0_ADDR_REG (0xB100)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_0_ITERATION_REG (0xB101)
|
||||
|
||||
#define PATTERN_WAIT_0_ADDR_REG (0xB102)
|
||||
|
||||
#define PATTERN_WAIT_0_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB103)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB104)
|
||||
|
||||
#define PATTERN_LOOP_1_ADDR_REG (0xB105)
|
||||
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_1_ITERATION_REG (0xB106)
|
||||
|
||||
#define PATTERN_WAIT_1_ADDR_REG (0xB107)
|
||||
|
||||
#define PATTERN_WAIT_1_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB108)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB109)
|
||||
|
||||
#define PATTERN_LOOP_2_ADDR_REG (0xB10A)
|
||||
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_2_ITERATION_REG (0xB10B)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_REG (0xB10C)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB10D)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB10E)
|
||||
|
||||
#define PATTERN_LOOP_3_ADDR_REG (0xB10F)
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#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_3_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
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#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
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#define PATTERN_LOOP_3_ITERATION_REG (0xB110)
|
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|
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#define PATTERN_WAIT_3_ADDR_REG (0xB111)
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|
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#define PATTERN_WAIT_3_ADDR_OFST (0)
|
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#define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST)
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|
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#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB112)
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|
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#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB113)
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|
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#define PATTERN_LOOP_4_ADDR_REG (0xB114)
|
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|
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#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
|
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#define PATTERN_LOOP_4_ADDR_STRT_MSK \
|
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(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
|
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#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
|
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#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
|
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|
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#define PATTERN_LOOP_4_ITERATION_REG (0xB115)
|
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|
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#define PATTERN_WAIT_4_ADDR_REG (0xB116)
|
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|
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#define PATTERN_WAIT_4_ADDR_OFST (0)
|
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#define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST)
|
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|
||||
#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB117)
|
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|
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#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB118)
|
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|
||||
#define PATTERN_LOOP_5_ADDR_REG (0xB119)
|
||||
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_5_ITERATION_REG (0xB11A)
|
||||
|
||||
#define PATTERN_WAIT_5_ADDR_REG (0xB11B)
|
||||
#define PATTERN_WAIT_5_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST)
|
||||
#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB11C)
|
||||
#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB11D)
|
||||
Reference in New Issue
Block a user