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Dev: m3 clkdiv0 20 (#924)

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* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max
This commit is contained in:
maliakal_d
2024-07-25 17:18:45 +02:00
committed by GitHub
parent bf523c0c5e
commit ce7f01bdc4
5 changed files with 9 additions and 3 deletions
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4
slsSupportLib/include/sls/versionAPI.h
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@ -8,9 +8,7 @@
#define APIGOTTHARD "developer 0x240207"
#define APIGOTTHARD2 "developer 0x240207"
#define APIJUNGFRAU "developer 0x240207"
#define APIMYTHEN3 "developer 0x240207"
#define APIMOENCH "developer 0x240207"
#define APIXILINXCTB "developer 0x240207"
#define APIEIGER "developer 0x240207"
#define APIMOENCH "developer 0x240703"
#define APIMOENCH "developer 0x240703"
#define APIMYTHEN3 "developer 0x240715"