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Dev: m3 clkdiv0 20 (#924)

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* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max
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maliakal_d
2024-07-25 17:18:45 +02:00
committed by GitHub
parent bf523c0c5e
commit ce7f01bdc4
5 changed files with 9 additions and 3 deletions
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2
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -65,6 +65,8 @@
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
#define DEFAULT_READOUT_C0_STARTUP (20) //(50000000) // rdo_clk, 50 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
#define DEFAULT_ADIF_PIPELINE_VAL (8)