Dev: m3 clkdiv0 20 (#924)

Browse Source

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max

...

This commit is contained in:

maliakal_d

2024-07-25 17:18:45 +02:00

committed by GitHub

parent bf523c0c5e

commit ce7f01bdc4

5 changed files with 9 additions and 3 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download Patch File Download Diff File Expand all files Collapse all files

BIN

slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer

Binary file not shown.