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This commit is contained in:
maliakal_d
2020-05-19 18:24:32 +02:00
parent 4570ffc8ad
commit cd90f09a30
15 changed files with 966 additions and 92 deletions
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70
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@ -19,9 +19,6 @@
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
/* ASIC Control */
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_010F
/* ASIC Digital Interface. Data recovery core */
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd
@ -33,14 +30,21 @@
#define BASE_PKT (0x0130) // 0x1806_0130 - 0x1806_013F
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/pkt/pkt_ctrl.vhd
/* Pattern control and status registers */
/* ASIC Exposure Control */
#define BASE_ASIC_EXP (0x0180) // 0x1806_0180 - 0x1806_01BF
/* Pattern control and status */
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd
/* Flow control and status registers */
/* Flow control and status */
#define BASE_FLOW_CONTROL (0x00400) // 0x1806_0400 - 0x1806_04FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/qsys/flow/flow_ctrl.vhd
/** ASIC Readout Control */
#define BASE_ASIC_RDO (0x00500) // 0x1806_0500 - 0x1806_050F
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/asic_rdo/asic_rdo.vhd
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
@ -157,6 +161,53 @@
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* ASIC Exposure Control registers
* --------------------------------------------------*/
/** ASIC Exposure Status register */
#define ASIC_EXP_STATUS_REG (0x00 * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_STAT_GATE_SRC_EXT_OFST (0)
#define ASIC_EXP_STAT_GATE_SRC_EXT_MSK (0x00000001 << ASIC_EXP_STAT_GATE_SRC_EXT_OFST)
#define ASIC_EXP_STAT_STO_LNGTH_OFST (16)
#define ASIC_EXP_STAT_STO_LNGTH_MSK (0x000000FF << ASIC_EXP_STAT_STO_LNGTH_OFST)
#define ASIC_EXP_STAT_RSCNTR_LNGTH_OFST (24)
#define ASIC_EXP_STAT_RSCNTR_LNGTH_MSK (0x000000FF << ASIC_EXP_STAT_RSCNTR_LNGTH_OFST)
/** Gate 0 width register */
#define ASIC_EXP_GATE_0_WIDTH_LSB_REG (0x01 * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_GATE_0_WIDTH_MSB_REG (0x02 * REG_OFFSET + BASE_ASIC_EXP)
/** Gate 1 width register */
#define ASIC_EXP_GATE_1_WIDTH_LSB_REG (0x03 * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_GATE_1_WIDTH_MSB_REG (0x04 * REG_OFFSET + BASE_ASIC_EXP)
/** Gate 2 width register */
#define ASIC_EXP_GATE_2_WIDTH_LSB_REG (0x05 * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_GATE_2_WIDTH_MSB_REG (0x06 * REG_OFFSET + BASE_ASIC_EXP)
/** Gate 0 delay register */
#define ASIC_EXP_GATE_0_DELAY_LSB_REG (0x07 * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_GATE_0_DELAY_MSB_REG (0x08 * REG_OFFSET + BASE_ASIC_EXP)
/** Gate 1 delay register */
#define ASIC_EXP_GATE_1_DELAY_LSB_REG (0x09 * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_GATE_1_DELAY_MSB_REG (0x0A * REG_OFFSET + BASE_ASIC_EXP)
/** Gate 2 delay register */
#define ASIC_EXP_GATE_2_DELAY_LSB_REG (0x0B * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_GATE_2_DELAY_MSB_REG (0x0C * REG_OFFSET + BASE_ASIC_EXP)
/** Gate period register */
#define ASIC_EXP_GATE_PERIOD_LSB_REG (0x0D * REG_OFFSET + BASE_ASIC_EXP)
#define ASIC_EXP_GATE_PERIOD_MSB_REG (0x0E * REG_OFFSET + BASE_ASIC_EXP)
/** Number of Internal Gates register */
#define ASIC_EXP_INT_GATE_NUMBER_REG (0x0F * REG_OFFSET + BASE_ASIC_EXP)
/** Number of Internal Gates register */
#define ASIC_EXP_EXT_GATE_NUMBER_REG (0x10 * REG_OFFSET + BASE_ASIC_EXP)
/* Pattern Control registers
* --------------------------------------------------*/
@ -325,4 +376,13 @@
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_FLOW_CONTROL)
/* ASIC Readout Control registers
* --------------------------------------------------*/
#define ASIC_RDO_CONFIG_REG (0x01 * REG_OFFSET + BASE_ASIC_RDO)
#define ASICRDO_CNFG_RESSTRG_LNGTH_OFST (0)
#define ASICRDO_CNFG_RESSTRG_LNGTH_MSK (0x000000FF << ASICRDO_CNFG_RESSTRG_LNGTH_OFST)
// clang-format on

280
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

@ -415,6 +415,7 @@ void setupDetector() {
// defaults
setHighVoltage(DEFAULT_HIGH_VOLTAGE);
setDefaultDacs();
setASICDefaults();
// dynamic range
setDynamicRange(DEFAULT_DYNAMIC_RANGE);
@ -424,10 +425,15 @@ void setupDetector() {
// Initialization of acquistion parameters
setNumFrames(DEFAULT_NUM_FRAMES);
setNumTriggers(DEFAULT_NUM_CYCLES);
setExpTime(DEFAULT_EXPTIME);
setPeriod(DEFAULT_PERIOD);
setDelayAfterTrigger(DEFAULT_DELAY_AFTER_TRIGGER);
setTiming(DEFAULT_TIMING_MODE);
setNumIntGates(DEFAULT_INTERNAL_GATES);
setNumGates(DEFAULT_EXTERNAL_GATES);
for (int i = 0; i != 2; ++i) {
setExpTime(i, DEFAULT_GATE_WIDTH);
setGateDelay(i, DEFAULT_GATE_DELAY);
}
}
int setDefaultDacs() {
@ -446,6 +452,25 @@ int setDefaultDacs() {
return ret;
}
void setASICDefaults() {
uint32_t val = bus_r(ASIC_EXP_STATUS_REG);
val &= (~ASIC_EXP_STAT_STO_LNGTH_MSK);
val |= ((DEFAULT_ASIC_LATCHING_NUM_PULSES << ASIC_EXP_STAT_STO_LNGTH_OFST) &
ASIC_EXP_STAT_STO_LNGTH_MSK);
val &= (~ASIC_EXP_STAT_RSCNTR_LNGTH_MSK);
val |=
((DEFAULT_ASIC_LATCHING_NUM_PULSES << ASIC_EXP_STAT_RSCNTR_LNGTH_OFST) &
ASIC_EXP_STAT_RSCNTR_LNGTH_MSK);
bus_w(ASIC_EXP_STATUS_REG, val);
val = bus_r(ASIC_RDO_CONFIG_REG);
val &= (~ASICRDO_CNFG_RESSTRG_LNGTH_MSK);
val |=
((DEFAULT_ASIC_LATCHING_NUM_PULSES << ASICRDO_CNFG_RESSTRG_LNGTH_OFST) &
ASICRDO_CNFG_RESSTRG_LNGTH_MSK);
bus_w(ASIC_RDO_CONFIG_REG, val);
}
/* firmware functions (resets) */
void cleanFifos() {
@ -783,40 +808,18 @@ int64_t getNumTriggers() {
return get64BitReg(SET_CYCLES_LSB_REG, SET_CYCLES_MSB_REG);
}
int setExpTime(int64_t val) {
if (val < 0) {
LOG(logERROR, ("Invalid exptime: %lld ns\n", (long long int)val));
return FAIL;
}
LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val));
val *= (1E-9 * getFrequency(SYSTEM_C0));
setPatternWaitTime(0, val);
// validate for tolerance
int64_t retval = getExpTime();
val /= (1E-9 * getFrequency(SYSTEM_C0));
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getExpTime() {
return setPatternWaitTime(0, -1) / (1E-9 * getFrequency(SYSTEM_C0));
}
int setPeriod(int64_t val) {
if (val < 0) {
LOG(logERROR, ("Invalid period: %lld ns\n", (long long int)val));
return FAIL;
}
LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
val *= (1E-9 * FIXED_PLL_FREQUENCY);
val *= (1E-9 * getFrequency(SYSTEM_C2));
set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
// validate for tolerance
int64_t retval = getPeriod();
val /= (1E-9 * FIXED_PLL_FREQUENCY);
val /= (1E-9 * getFrequency(SYSTEM_C2));
if (val != retval) {
return FAIL;
}
@ -825,7 +828,165 @@ int setPeriod(int64_t val) {
int64_t getPeriod() {
return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG) /
(1E-9 * FIXED_PLL_FREQUENCY);
(1E-9 * getFrequency(SYSTEM_C2));
}
void setNumIntGates(int val) {
if (val > 0) {
LOG(logINFO,
("Setting number of Internal Gates %lld\n", (long long int)val));
bus_w(ASIC_EXP_INT_GATE_NUMBER_REG, val);
}
}
void setNumGates(int val) {
if (val > 0) {
LOG(logINFO, ("Setting number of Gates %lld\n", (long long int)val));
bus_w(ASIC_EXP_EXT_GATE_NUMBER_REG, val);
}
}
int getNumExtGates() { return bus_r(ASIC_EXP_EXT_GATE_NUMBER_REG); }
void updateGatePeriod() {
uint64_t max = 0;
for (int i = 0; i != 2; ++i) {
// TODO: only those counters enabled (when updated to mask in firmware)
uint64_t sum = getExpTime(i) + getGateDelay(i);
if (sum > max) {
max = sum;
}
}
LOG(logINFO, ("\tSetting Gate Period to %lld ns\n", (long long int)max));
max *= (1E-9 * getFrequency(SYSTEM_C2));
set64BitReg(max, ASIC_EXP_GATE_PERIOD_LSB_REG,
ASIC_EXP_GATE_PERIOD_MSB_REG);
}
int setExptime(int gateIndex, int64_t val) {
uint32_t alsb = 0;
uint32_t amsb = 0;
switch (gateIndex) {
case 0:
alsb = ASIC_EXP_GATE_0_WIDTH_LSB_REG;
blsb = ASIC_EXP_GATE_0_WIDTH_MSB_REG;
break;
case 1:
alsb = ASIC_EXP_GATE_1_WIDTH_LSB_REG;
blsb = ASIC_EXP_GATE_1_WIDTH_MSB_REG;
break;
case 2:
alsb = ASIC_EXP_GATE_2_WIDTH_LSB_REG;
blsb = ASIC_EXP_GATE_2_WIDTH_MSB_REG;
break;
default:
LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
return FAIL;
}
if (val < 0) {
LOG(logERROR, ("Invalid exptime (index:%d): %lld ns\n", gateIndex,
(long long int)val));
return FAIL;
}
LOG(logINFO, ("Setting exptime %lld ns (index:%d)\n", (long long int)val,
gateIndex));
val *= (1E-9 * getFrequency(SYSTEM_C2));
set64BitReg(val, alsb, amsb);
// validate for tolerance
int64_t retval = getExpTime(gateIndex);
val /= (1E-9 * getFrequency(SYSTEM_C2));
if (val != retval) {
return FAIL;
}
updateGatePeriod();
return OK;
}
int64_t getExptime(int gateIndex) {
switch (gateIndex) {
case 0:
alsb = ASIC_EXP_GATE_0_WIDTH_LSB_REG;
blsb = ASIC_EXP_GATE_0_WIDTH_MSB_REG;
break;
case 1:
alsb = ASIC_EXP_GATE_1_WIDTH_LSB_REG;
blsb = ASIC_EXP_GATE_1_WIDTH_MSB_REG;
break;
case 2:
alsb = ASIC_EXP_GATE_2_WIDTH_LSB_REG;
blsb = ASIC_EXP_GATE_2_WIDTH_MSB_REG;
break;
default:
LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
return -1;
}
return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C2));
}
int setGateDelay(int gateIndex, int64_t val) {
uint32_t alsb = 0;
uint32_t amsb = 0;
switch (gateIndex) {
case 0:
alsb = ASIC_EXP_GATE_0_DELAY_LSB_REG;
blsb = ASIC_EXP_GATE_0_DELAY_MSB_REG;
break;
case 1:
alsb = ASIC_EXP_GATE_1_DELAY_LSB_REG;
blsb = ASIC_EXP_GATE_1_DELAY_MSB_REG;
break;
case 2:
alsb = ASIC_EXP_GATE_2_DELAY_LSB_REG;
blsb = ASIC_EXP_GATE_2_DELAY_MSB_REG;
break;
default:
LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
return FAIL;
}
if (val < 0) {
LOG(logERROR, ("Invalid gate delay (index:%d): %lld ns\n", gateIndex,
(long long int)val));
return FAIL;
}
LOG(logINFO, ("Setting gate delay %lld ns (index:%d)\n", (long long int)val,
gateIndex));
val *= (1E-9 * getFrequency(SYSTEM_C2));
set64BitReg(val, alsb, amsb);
// validate for tolerance
int64_t retval = getGateDelay(gateIndex);
val /= (1E-9 * getFrequency(SYSTEM_C2));
if (val != retval) {
return FAIL;
}
updateGatePeriod();
return OK;
}
int64_t getGateDelay(int gateIndex) {
switch (gateIndex) {
case 0:
alsb = ASIC_EXP_GATE_0_DELAY_LSB_REG;
blsb = ASIC_EXP_GATE_0_DELAY_MSB_REG;
break;
case 1:
alsb = ASIC_EXP_GATE_1_DELAY_LSB_REG;
blsb = ASIC_EXP_GATE_1_DELAY_MSB_REG;
break;
case 2:
alsb = ASIC_EXP_GATE_2_DELAY_LSB_REG;
blsb = ASIC_EXP_GATE_2_DELAY_MSB_REG;
break;
default:
LOG(logERROR, ("Invalid gate index: %d\n", gateIndex));
return -1;
}
return get64BitReg(alsb, amsb) / (1E-9 * getFrequency(SYSTEM_C2));
}
void setCounterMask(uint32_t arg) {
@ -852,6 +1013,8 @@ void setCounterMask(uint32_t arg) {
bus_w(addr, bus_r(addr) & ~CONFIG_COUNTER_ENA_MSK);
bus_w(addr, bus_r(addr) | val);
LOG(logDEBUG, ("Config Reg: 0x%x\n", bus_r(addr)));
updateGatePeriod();
}
uint32_t getCounterMask() {
@ -897,12 +1060,12 @@ int setDelayAfterTrigger(int64_t val) {
return FAIL;
}
LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
val *= (1E-9 * FIXED_PLL_FREQUENCY);
val *= (1E-9 * getFrequency(SYSTEM_C2));
set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
// validate for tolerance
int64_t retval = getDelayAfterTrigger();
val /= (1E-9 * FIXED_PLL_FREQUENCY);
val /= (1E-9 * getFrequency(SYSTEM_C2));
if (val != retval) {
return FAIL;
}
@ -911,7 +1074,7 @@ int setDelayAfterTrigger(int64_t val) {
int64_t getDelayAfterTrigger() {
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) /
(1E-9 * FIXED_PLL_FREQUENCY);
(1E-9 * getFrequency(SYSTEM_C2));
}
int64_t getNumFramesLeft() {
@ -924,12 +1087,12 @@ int64_t getNumTriggersLeft() {
int64_t getDelayAfterTriggerLeft() {
return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) /
(1E-9 * FIXED_PLL_FREQUENCY);
(1E-9 * getFrequency(SYSTEM_C2));
}
int64_t getPeriodLeft() {
return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) /
(1E-9 * FIXED_PLL_FREQUENCY);
(1E-9 * getFrequency(SYSTEM_C2));
}
int64_t getFramesFromStart() {
@ -1014,23 +1177,68 @@ void setTiming(enum timingMode arg) {
if (arg != GET_TIMING_MODE) {
switch (arg) {
case AUTO_TIMING:
LOG(logINFO, ("Set Timing: Auto\n"));
LOG(logINFO, ("Set Timing: Auto (Int. Trigger, Int. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break;
case TRIGGER_EXPOSURE:
LOG(logINFO, ("Set Timing: Trigger\n"));
LOG(logINFO, ("Set Timing: Trigger (Ext. Trigger, Int. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) & ~ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break;
case GATED:
LOG(logINFO, ("Set Timing: Gating (Int. Trigger, Ext. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break;
case TRIGGER_GATED:
LOG(logINFO,
("Set Timing: Trigger_Gating (Ext. Trigger, Ext. Gating)\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
bus_w(ASIC_EXP_STATUS_REG,
bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
break;
default:
LOG(logERROR, ("Unknown timing mode %d\n", arg));
return;
}
// internal gating
if (arg == AUTO_TIMING || arg == TRIGGER_EXPOSURE) {
setNumGates(1); // should be in firmware
// TOOD: number of counters-> set appropriate gatewidth and
// gatedelay to 0
setMaxGatePulseWidth();
}
// external gating
else {
}
}
}
enum timingMode getTiming() {
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
return TRIGGER_EXPOSURE;
return AUTO_TIMING;
uint32_t extTrigger = (bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
uint32_t extGate =
(bus_r(ASIC_EXP_STATUS_REG) | ASIC_EXP_STAT_GATE_SRC_EXT_MSK);
if (extTrigger) {
if (extGate) {
// external trigger, external gating
return TRIGGER_GATED;
} else {
// external trigger, internal gating
return TRIGGER_EXPOSURE;
}
} else {
if (extGate) {
// internal trigger, external gating
return GATED;
} else {
// internal trigger, internal gating
return AUTO_TIMING;
}
}
}
int configureMAC() {

30
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
View File

@ -23,19 +23,23 @@
#define TYPE_NO_MODULE_STARTING_VAL (800)
/** Default Parameters */
#define DEFAULT_DYNAMIC_RANGE (24)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (100 * 1000 * 1000) // ns
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (5) //(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
#define DEFAULT_INTERNAL_GATES (1)
#define DEFAULT_EXTERNAL_GATES (1)
#define DEFAULT_DYNAMIC_RANGE (24)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_GATE_WIDTH (100 * 1000 * 1000) // ns
#define DEFAULT_GATE_DELAY (0)
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (5) //(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)