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formatting (#716)

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* formatting
This commit is contained in:
Dhanya Thattil
2023-04-12 15:30:34 +02:00
committed by GitHub
parent a5022ff0ee
commit cb4f733350
4 changed files with 588 additions and 535 deletions
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44
slsDetectorServers/ctbDetectorServer/RegisterDefs.h
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@ -622,11 +622,9 @@
#define PATTERN_WAIT_TIMER_5_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_5_MSB_REG (0x92 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value RO register */
#define ADC_SLOW_DATA_REG (0x93 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value Config register */
#define ADC_SLOW_CFG_REG (0x94 << MEM_MAP_SHIFT)
/** Read back CFG Register */
@ -636,13 +634,13 @@
/** Channel sequencer */
#define ADC_SLOW_CFG_SEQ_OFST (3)
#define ADC_SLOW_CFG_SEQ_MSK (0x00000003 << ADC_SLOW_CFG_SEQ_OFST)
#define ADC_SLOW_CFG_SEQ_DSBLE_VAL \
#define ADC_SLOW_CFG_SEQ_DSBLE_VAL \
((0x0 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
#define ADC_SLOW_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL \
#define ADC_SLOW_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL \
((0x1 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
#define ADC_SLOW_CFG_SEQ_SCN_WTH_TMP_VAL \
#define ADC_SLOW_CFG_SEQ_SCN_WTH_TMP_VAL \
((0x2 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
#define ADC_SLOW_CFG_SEQ_SCN_WTHT_TMP_VAL \
#define ADC_SLOW_CFG_SEQ_SCN_WTHT_TMP_VAL \
((0x3 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
/** Reference/ buffer selection */
@ -650,32 +648,33 @@
#define ADC_SLOW_CFG_REF_MSK (0x00000007 << ADC_SLOW_CFG_REF_OFST)
/** Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
*/
#define ADC_SLOW_CFG_REF_INT_2500MV_VAL \
#define ADC_SLOW_CFG_REF_INT_2500MV_VAL \
((0x0 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_OFST)
/** Internal reference. REF = 4.096V buffered output. Temperature sensor
* enabled. */
#define ADC_SLOW_CFG_REF_INT_4096MV_VAL \
#define ADC_SLOW_CFG_REF_INT_4096MV_VAL \
((0x1 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer disabled. */
#define ADC_SLOW_CFG_REF_EXT_TMP_VAL \
#define ADC_SLOW_CFG_REF_EXT_TMP_VAL \
((0x2 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer enabled. */
#define ADC_SLOW_CFG_REF_EXT_TMP_INTBUF_VAL \
#define ADC_SLOW_CFG_REF_EXT_TMP_INTBUF_VAL \
((0x3 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer disabled.
*/
#define ADC_SLOW_CFG_REF_EXT_VAL \
#define ADC_SLOW_CFG_REF_EXT_VAL \
((0x6 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer enabled. */
#define ADC_SLOW_CFG_REF_EXT_INTBUF_VAL \
#define ADC_SLOW_CFG_REF_EXT_INTBUF_VAL \
((0x7 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** bandwidth of low pass filter */
#define ADC_SLOW_CFG_BW_OFST (8)
#define ADC_SLOW_CFG_BW_MSK (0x00000001 << ADC_SLOW_CFG_REF_OFST)
#define ADC_SLOW_CFG_BW_ONE_FOURTH_VAL \
#define ADC_SLOW_CFG_BW_ONE_FOURTH_VAL \
((0x0 << ADC_SLOW_CFG_BW_OFST) & ADC_SLOW_CFG_BW_MSK)
#define ADC_SLOW_CFG_BW_FULL_VAL ((0x1 << ADC_SLOW_CFG_BW_OFST) & ADC_SLOW_CFG_BW_MSK)
#define ADC_SLOW_CFG_BW_FULL_VAL \
((0x1 << ADC_SLOW_CFG_BW_OFST) & ADC_SLOW_CFG_BW_MSK)
/** input channel selection IN0 - IN7 */
#define ADC_SLOW_CFG_IN_OFST (9)
@ -684,28 +683,27 @@
/** input channel configuration */
#define ADC_SLOW_CFG_INCC_OFST (12)
#define ADC_SLOW_CFG_INCC_MSK (0x00000007 << ADC_SLOW_CFG_INCC_OFST)
#define ADC_SLOW_CFG_INCC_BPLR_DFFRNTL_PRS_VAL \
#define ADC_SLOW_CFG_INCC_BPLR_DFFRNTL_PRS_VAL \
((0x0 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_BPLR_IN_COM_VAL \
#define ADC_SLOW_CFG_INCC_BPLR_IN_COM_VAL \
((0x2 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_TMP_VAL \
#define ADC_SLOW_CFG_INCC_TMP_VAL \
((0x3 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL \
#define ADC_SLOW_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL \
((0x4 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_UNPLR_IN_COM_VAL \
#define ADC_SLOW_CFG_INCC_UNPLR_IN_COM_VAL \
((0x6 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_UNPLR_IN_GND_VAL \
#define ADC_SLOW_CFG_INCC_UNPLR_IN_GND_VAL \
((0x7 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
/** configuration update */
#define ADC_SLOW_CFG_CFG_OFST (15)
#define ADC_SLOW_CFG_CFG_MSK (0x00000001 << ADC_SLOW_CFG_CFG_OFST)
#define ADC_SLOW_CFG_CFG_NO_UPDATE_VAL \
#define ADC_SLOW_CFG_CFG_NO_UPDATE_VAL \
((0x0 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
#define ADC_SLOW_CFG_CFG_OVRWRTE_VAL \
#define ADC_SLOW_CFG_CFG_OVRWRTE_VAL \
((0x1 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
/* Slow ADC SPI Value Control register */
#define ADC_SLOW_CTRL_REG (0x95 << MEM_MAP_SHIFT)