jungfrau detector server starts in CPU_NOT_10GB mode; ADC VREF put to 1V

This commit is contained in:
bergamaschi 2015-02-10 10:16:43 +01:00
parent 4f84bb19da
commit c69ddad821
2 changed files with 8 additions and 6 deletions

View File

@ -1039,15 +1039,15 @@ int startReceiver(int start) {
int reg=bus_r(addr); int reg=bus_r(addr);
//for start recever, write 0 and for stop, write 1 //for start recever, write 0 and for stop, write 1
if (!start) if (!start)
bus_w(CONFIG_REG,reg|CPU_OR_RECEIVER_BIT); bus_w(CONFIG_REG,reg&(~GB10_NOT_CPU_BIT));
else else
bus_w(CONFIG_REG,reg&(~CPU_OR_RECEIVER_BIT)); bus_w(CONFIG_REG,reg|GB10_NOT_CPU_BIT);
reg=bus_r(addr); reg=bus_r(addr);
//#ifdef VERBOSE //#ifdef VERBOSE
printf("Config Reg %x\n", reg); printf("Config Reg %x\n", reg);
//#endif //#endif
int d =reg&CPU_OR_RECEIVER_BIT; int d =reg&GB10_NOT_CPU_BIT;
if(d!=0) d=1; if(d!=0) d=1;
if(d!=start) if(d!=start)
return OK; return OK;
@ -2279,8 +2279,6 @@ int prepareADC(){
codata=0; codata=0;
writeADC(0x08,0x3); writeADC(0x08,0x3);
writeADC(0x08,0x0); writeADC(0x08,0x0);
writeADC(0x14,0x40);//lvds reduced range
// writeADC(0x14,0x00);//lvds
writeADC(0x16,0x01);//output clock phase writeADC(0x16,0x01);//output clock phase
@ -2288,6 +2286,10 @@ int prepareADC(){
// writeADC(0x16,0x4);//output clock phase // writeADC(0x16,0x4);//output clock phase
writeADC(0x18,0x0);// vref 1V
writeADC(0x14,0x40);//lvds reduced range -- offset binary
writeADC(0xD,0x0);//no test mode writeADC(0xD,0x0);//no test mode
#ifdef TESTADC #ifdef TESTADC

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@ -392,7 +392,7 @@
#define TOT_ENABLE_BIT 0x00000002 #define TOT_ENABLE_BIT 0x00000002
#define TIMED_GATE_BIT 0x00000004 #define TIMED_GATE_BIT 0x00000004
#define CONT_RO_ENABLE_BIT 0x00080000 #define CONT_RO_ENABLE_BIT 0x00080000
#define CPU_OR_RECEIVER_BIT 0x00001000 #define GB10_NOT_CPU_BIT 0x00001000