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m3:changed str_clk (clkdiv 3) default to 166MHz (6) (#643)

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Dhanya Thattil
2023-01-30 17:05:42 +01:00
committed by GitHub
parent 3a3628c475
commit c62ce0ce6b
3 changed files with 2 additions and 2 deletions
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slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv7.0.0.rc3
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slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -60,7 +60,7 @@
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // rdo_smp_clk, 100 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (8) //(125000000) // str_clk, 125 MHz const
#define DEFAULT_SYSTEM_C1 (6) //(166666666) // str_clk, 166 MHz const
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz