mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-21 17:18:00 +02:00
1. Ctb transceiver ro (#773)
* transceiverenable, tsamples, romode for tranceiver and digital_transceiver * 202 spec instr only for transceiver mode * removed check for empty in trans readout and clean memory before reading from fifo * ctb read fifo strobe for all after reading all channels, adding 1us after selecting channel, changing fw date * updated 10gb transceiver enable ---- * added transceiver (tsamples, romode(transceiver, digital_transceiver), transceiverenable (mask) * clean memory before reading from fifo (for analog and digital as well) * read fifo then read strobe (also corresp fw) fixes number of reads (also for analg and digital)-> increases all pipelines by 1 * fixed bug in rearranging digital data in receiver * fixed bug in streaming size of data after rearranging * fixed bug in setbit, clearbit,and getbit * status checks fifo before returning idle (transmitting if data in fifo if transceiver more enabled) * soem matterhorn specifics that will need to be put into pattern in a month or two. this is temporary. * NOTE: breaking api. rxParameters struct has transceiverenabel and tsamples given from det to receiver
This commit is contained in:
GitHub
@ -1,6 +1,7 @@
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// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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// clang-format off
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/* Definitions for FPGA */
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#define MEM_MAP_SHIFT 1
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@ -87,7 +88,7 @@
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/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
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* PLL_PARAM_REG 0x50 */
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//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
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// #define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
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/* FIFO Data RO register TODO */
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#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
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@ -95,8 +96,9 @@
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#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
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#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
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(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
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//#define FIFO_DATA_WRD_OFST (16)
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//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
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// #define FIFO_DATA_WRD_OFST (16)
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// #define FIFO_DATA_WRD_MSK (0x0000FFFF <<
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// FIFO_DATA_WRD_OFST)
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/* FIFO Status RO register TODO */
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#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
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@ -146,15 +148,15 @@
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#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
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/* Exposure Time Left 64 bit RO register */
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//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
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// used in FW #define EXPTIME_LEFT_MSB_REG (0x1B <<
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// MEM_MAP_SHIFT)
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// #define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
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// used in FW #define EXPTIME_LEFT_MSB_REG (0x1B <<
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// MEM_MAP_SHIFT)
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//// Not used in FW
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/* Gates Left 64 bit RO register */
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//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
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// used in FW #define GATES_LEFT_MSB_REG (0x1D <<
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// MEM_MAP_SHIFT)
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// #define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
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// used in FW #define GATES_LEFT_MSB_REG (0x1D <<
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// MEM_MAP_SHIFT)
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//// Not used in FW
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/* Data In 64 bit RO register TODO */
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@ -184,14 +186,28 @@
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#define POWER_STATUS_ALRT_OFST (27)
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#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
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/* FIFO Transceiver In Status RO register */
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#define FIFO_TIN_STATUS_REG (0x30 << MEM_MAP_SHIFT)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST (4)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_1_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST (5)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_2_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_3_OFST (6)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_3_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_3_OFST)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST (7)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_4_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST)
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#define FIFO_TIN_STATUS_FIFO_EMPTY_ALL_MSK (0x0000000F << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
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/* FIFO Transceiver In 64 bit RO register */
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#define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT)
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#define FIFO_TIN_MSB_REG (0x32 << MEM_MAP_SHIFT)
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/* FIFO Digital In Status RO register */
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#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
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#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
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#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
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(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
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#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
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#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
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#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
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#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
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#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
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(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
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#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
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/* FIFO Digital In 64 bit RO register */
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#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
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@ -246,14 +262,16 @@
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/* Dummy RW register */
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#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
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#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
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#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
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#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
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#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
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(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
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#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
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#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
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(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
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#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
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#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
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#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
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#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
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#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
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#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
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#define DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_OFST (12)
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#define DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_MSK (0x00000003 << DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_OFST)
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#define DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST (14)
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#define DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST)
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/* Receiver IP Address RW register */
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#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
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@ -296,14 +314,17 @@
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/* Configuration RW register */
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#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
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#define CONFIG_LED_DSBL_OFST (0)
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#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
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#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
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#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
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#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
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#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
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#define CONFIG_GB10_SND_UDP_OFST (12)
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#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
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#define CONFIG_LED_DSBL_OFST (0)
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#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
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#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
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#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
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#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
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#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
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#define CONFIG_ENBLE_TRNSCVR_OTPT_OFST (10)
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#define CONFIG_ENBLE_TRNSCVR_OTPT_MSK \
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(0x00000001 << CONFIG_ENBLE_TRNSCVR_OTPT_OFST)
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#define CONFIG_GB10_SND_UDP_OFST (12)
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#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
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/* External Signal RW register */
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#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
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@ -320,33 +341,34 @@
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#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
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#define CONTROL_STP_ACQSTN_OFST (1)
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#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
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//#define CONTROL_STRT_FF_TST_OFST (2)
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//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
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// CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
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//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
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// CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
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//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
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// CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5)
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// #define CONTROL_STP_RDT_MSK (0x00000001 <<
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// CONTROL_STP_RDT_OFST)
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// #define CONTROL_STRT_FF_TST_OFST (2)
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// #define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
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// CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
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// #define CONTROL_STP_FF_TST_MSK (0x00000001 <<
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// CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
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// #define CONTROL_STRT_RDT_MSK (0x00000001 <<
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// CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5)
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// #define CONTROL_STP_RDT_MSK (0x00000001 <<
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// CONTROL_STP_RDT_OFST)
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#define CONTROL_STRT_EXPSR_OFST (6)
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#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
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//#define CONTROL_STP_EXPSR_OFST (7)
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//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
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// CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
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// CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
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//#define CONTROL_STP_TRN_OFST (9)
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//#define CONTROL_STP_TRN_MSK (0x00000001 <<
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// CONTROL_STP_RDT_OFST)
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// #define CONTROL_STP_EXPSR_OFST (7)
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// #define CONTROL_STP_EXPSR_MSK (0x00000001 <<
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// CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8)
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// #define CONTROL_STRT_TRN_MSK (0x00000001 <<
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// CONTROL_STRT_RDT_OFST)
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// #define CONTROL_STP_TRN_OFST (9)
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// #define CONTROL_STP_TRN_MSK (0x00000001 <<
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// CONTROL_STP_RDT_OFST)
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#define CONTROL_CRE_RST_OFST (10)
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#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
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#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
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#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
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#define CONTROL_MMRY_RST_OFST (12)
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#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
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//#define CONTROL_PLL_RCNFG_WR_OFST (13)
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//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
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// CONTROL_PLL_RCNFG_WR_OFST)
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// #define CONTROL_PLL_RCNFG_WR_OFST (13)
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// #define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
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// CONTROL_PLL_RCNFG_WR_OFST)
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#define CONTROL_SND_10GB_PCKT_OFST (14)
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#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
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#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
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@ -457,8 +479,10 @@
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#define POWER_HV_INTERNAL_SLCT_OFST (31)
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#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
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/* Number of Words RW register TODO */
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#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
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/* Number of samples from transceiver RW register */
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#define SAMPLES_TRANSCEIVER_REG (0x5F << MEM_MAP_SHIFT)
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#define SAMPLES_TRANSCEIVER_OFST (0)
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#define SAMPLES_TRANSCEIVER_MSK (0x0000FFFF << SAMPLES_TRANSCEIVER_OFST)
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/* Delay 64 bit RW register. t = DLY x 50 ns. */
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#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
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@ -477,14 +501,15 @@
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#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
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/* Period 64 bit RW register */
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//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
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// Not used in FW #define EXPTIME_MSB_REG (0x69 <<
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// MEM_MAP_SHIFT) // Not used in FW
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// #define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
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// Not used in FW #define EXPTIME_MSB_REG (0x69 <<
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// MEM_MAP_SHIFT) // Not used in FW
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/* Gates 64 bit RW register */
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//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
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// in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
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// Not used in FW
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// #define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not
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// used
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// in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
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// Not used in FW
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/* Pattern IO Control 64 bit RW regiser
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* Each bit configured as output(1)/ input(0) */
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@ -516,10 +541,13 @@
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/* Readout enable RW register */
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#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
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#define READOUT_10G_ENABLE_ANLG_OFST (0)
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#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
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#define READOUT_10G_ENABLE_DGTL_OFST (8)
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#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
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#define READOUT_10G_ENABLE_ANLG_OFST (0)
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#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
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#define READOUT_10G_ENABLE_DGTL_OFST (8)
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#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
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#define READOUT_10G_ENABLE_TRNSCVR_OFST (9)
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#define READOUT_10G_ENABLE_TRNSCVR_MSK \
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(0x0000000F << READOUT_10G_ENABLE_TRNSCVR_OFST)
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/* Digital Bit External Trigger RW register */
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#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
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@ -725,3 +753,5 @@
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/* Round Robin */
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#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
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// clang-format on
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Binary file not shown.
@ -50,15 +50,18 @@ pthread_t pthread_virtual_tid;
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int dataBytes = 0;
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int analogDataBytes = 0;
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int digitalDataBytes = 0;
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int transceiverDataBytes = 0;
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char *analogData = 0;
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char *digitalData = 0;
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char *transceiverData = 0;
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char volatile *analogDataPtr = 0;
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char volatile *digitalDataPtr = 0;
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char volatile *transceiverDataPtr = 0;
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char udpPacketData[UDP_PACKET_DATA_BYTES + sizeof(sls_detector_header)];
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uint32_t adcEnableMask_1g = BIT32_MSK;
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// 10g readout
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uint8_t adcEnableMask_10g = 0xFF;
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uint32_t transceiverMask = DEFAULT_TRANSCEIVER_MASK;
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int32_t clkPhase[NUM_CLOCKS] = {};
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uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200};
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@ -68,8 +71,10 @@ int vLimit = 0;
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int highvoltage = 0;
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int analogEnable = 1;
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int digitalEnable = 0;
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int transceiverEnable = 0;
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int naSamples = 1;
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int ndSamples = 1;
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int ntSamples = 1;
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int detPos[2] = {0, 0};
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int isInitCheckDone() { return initCheckDone; }
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@ -468,6 +473,7 @@ void setupDetector() {
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dataBytes = 0;
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analogDataBytes = 0;
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digitalDataBytes = 0;
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transceiverDataBytes = 0;
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if (analogData) {
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free(analogData);
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analogData = 0;
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@ -476,8 +482,13 @@ void setupDetector() {
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free(digitalData);
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digitalData = 0;
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}
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if (transceiverData) {
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free(transceiverData);
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transceiverData = 0;
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}
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analogDataPtr = 0;
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digitalDataPtr = 0;
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transceiverData = 0;
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{
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for (int i = 0; i < NUM_CLOCKS; ++i) {
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clkPhase[i] = 0;
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@ -493,10 +504,13 @@ void setupDetector() {
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highvoltage = 0;
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adcEnableMask_1g = BIT32_MSK;
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adcEnableMask_10g = 0xFF;
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transceiverMask = DEFAULT_TRANSCEIVER_MASK;
|
||||
analogEnable = 1;
|
||||
digitalEnable = 0;
|
||||
transceiverEnable = 0;
|
||||
naSamples = 1;
|
||||
ndSamples = 1;
|
||||
ntSamples = 1;
|
||||
#ifdef VIRTUAL
|
||||
sharedMemory_setStatus(IDLE);
|
||||
initializePatternWord();
|
||||
@ -575,6 +589,7 @@ void setupDetector() {
|
||||
setNumAnalogSamples(DEFAULT_NUM_SAMPLES);
|
||||
setNumDigitalSamples(
|
||||
DEFAULT_NUM_SAMPLES); // update databytes and allocate ram
|
||||
setNumTransceiverSamples(DEFAULT_NUM_SAMPLES);
|
||||
setNumFrames(DEFAULT_NUM_FRAMES);
|
||||
setExpTime(DEFAULT_EXPTIME);
|
||||
setNumTriggers(DEFAULT_NUM_CYCLES);
|
||||
@ -583,6 +598,8 @@ void setupDetector() {
|
||||
setTiming(DEFAULT_TIMING_MODE);
|
||||
setADCEnableMask(BIT32_MSK);
|
||||
setADCEnableMask_10G(BIT32_MSK);
|
||||
setTransceiverEnableMask(DEFAULT_TRANSCEIVER_MASK);
|
||||
|
||||
if (setReadoutMode(ANALOG_ONLY) == FAIL) {
|
||||
strcpy(initErrorMessage,
|
||||
"Could not set readout mode to analog only.\n");
|
||||
@ -596,18 +613,22 @@ int updateDatabytesandAllocateRAM() {
|
||||
|
||||
int oldAnalogDataBytes = analogDataBytes;
|
||||
int oldDigitalDataBytes = digitalDataBytes;
|
||||
int oldTranceiverDataBytes = transceiverDataBytes;
|
||||
updateDataBytes();
|
||||
|
||||
// update only if change in databytes
|
||||
if (analogDataBytes == oldAnalogDataBytes &&
|
||||
digitalDataBytes == oldDigitalDataBytes) {
|
||||
LOG(logDEBUG1, ("RAM size (Analog:%d, Digital:%d) already allocated. "
|
||||
"Nothing to be done.\n",
|
||||
analogDataBytes, digitalDataBytes));
|
||||
digitalDataBytes == oldDigitalDataBytes &&
|
||||
transceiverDataBytes == oldTranceiverDataBytes) {
|
||||
LOG(logDEBUG1,
|
||||
("RAM size (Analog:%d, Digital:%d, Transceiver:%d) already "
|
||||
"allocated. Nothing to be done.\n",
|
||||
analogDataBytes, digitalDataBytes, transceiverDataBytes));
|
||||
return OK;
|
||||
}
|
||||
// Zero databytes
|
||||
if (analogDataBytes == 0 && digitalDataBytes == 0) {
|
||||
if (analogDataBytes == 0 && digitalDataBytes == 0 &&
|
||||
transceiverDataBytes == 0) {
|
||||
LOG(logERROR, ("Can not allocate RAM for 0 bytes.\n"));
|
||||
return FAIL;
|
||||
}
|
||||
@ -620,6 +641,10 @@ int updateDatabytesandAllocateRAM() {
|
||||
free(digitalData);
|
||||
digitalData = 0;
|
||||
}
|
||||
if (transceiverData) {
|
||||
free(transceiverData);
|
||||
transceiverData = 0;
|
||||
}
|
||||
// allocate RAM
|
||||
if (analogDataBytes) {
|
||||
analogData = malloc(analogDataBytes);
|
||||
@ -640,16 +665,29 @@ int updateDatabytesandAllocateRAM() {
|
||||
"Probable cause: Memory Leak.\n"));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO,
|
||||
("\tDigital RAM allocated to %d bytes\n", digitalDataBytes));
|
||||
}
|
||||
if (transceiverDataBytes) {
|
||||
transceiverData = malloc(transceiverDataBytes);
|
||||
// cannot malloc
|
||||
if (transceiverData == NULL) {
|
||||
LOG(logERROR,
|
||||
("Can not allocate transceiver data RAM for even 1 frame. "
|
||||
"Probable cause: Memory Leak.\n"));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("\tTransceiver RAM allocated to %d bytes\n",
|
||||
transceiverDataBytes));
|
||||
}
|
||||
|
||||
LOG(logINFO, ("\tDigital RAM allocated to %d bytes\n", digitalDataBytes));
|
||||
return OK;
|
||||
}
|
||||
|
||||
void updateDataBytes() {
|
||||
int nachans = 0, ndchans = 0;
|
||||
int nachans = 0, ndchans = 0, ntchans = 0;
|
||||
analogDataBytes = 0;
|
||||
digitalDataBytes = 0;
|
||||
transceiverDataBytes = 0;
|
||||
|
||||
// analog
|
||||
if (analogEnable) {
|
||||
@ -672,10 +710,20 @@ void updateDataBytes() {
|
||||
LOG(logINFO, ("\t#Digital Channels:%d, Databytes:%d\n", ndchans,
|
||||
digitalDataBytes));
|
||||
}
|
||||
|
||||
// transceiver
|
||||
if (transceiverEnable) {
|
||||
for (int ichan = 0; ichan < NCHAN_TRANSCEIVER; ++ichan) {
|
||||
if (transceiverMask & (1 << ichan))
|
||||
++ntchans;
|
||||
}
|
||||
transceiverDataBytes =
|
||||
ntchans * (NBITS_PER_TRANSCEIVER / 8) * ntSamples;
|
||||
LOG(logINFO, ("\t#Transceiver Channels:%d, Databytes:%d\n", ntchans,
|
||||
transceiverDataBytes));
|
||||
}
|
||||
// total
|
||||
int nchans = nachans + ndchans;
|
||||
dataBytes = analogDataBytes + digitalDataBytes;
|
||||
int nchans = nachans + ndchans + ntchans;
|
||||
dataBytes = analogDataBytes + digitalDataBytes + transceiverDataBytes;
|
||||
|
||||
LOG(logINFO,
|
||||
("\t#Total Channels:%d, Total Databytes:%d\n", nchans, dataBytes));
|
||||
@ -723,10 +771,6 @@ int getDynamicRange(int *retval) {
|
||||
}
|
||||
|
||||
int setADCEnableMask(uint32_t mask) {
|
||||
if (mask == 0u) {
|
||||
LOG(logERROR, ("Cannot set 1gb adc mask to 0\n"));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("Setting adcEnableMask 1G to 0x%08x\n", mask));
|
||||
adcEnableMask_1g = mask;
|
||||
// 1Gb enabled
|
||||
@ -792,6 +836,20 @@ uint32_t getADCEnableMask_10G() {
|
||||
return retval;
|
||||
}
|
||||
|
||||
int setTransceiverEnableMask(uint32_t mask) {
|
||||
LOG(logINFO, ("Setting transceivermask to 0x%08x\n", mask));
|
||||
transceiverMask = mask;
|
||||
// 1Gb enabled
|
||||
if (!enableTenGigabitEthernet(-1)) {
|
||||
if (updateDatabytesandAllocateRAM() == FAIL) {
|
||||
return FAIL;
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
uint32_t getTransceiverEnableMask() { return transceiverMask; }
|
||||
|
||||
void setADCInvertRegister(uint32_t val) {
|
||||
LOG(logINFO, ("Setting ADC Port Invert Reg to 0x%x\n", val));
|
||||
bus_w(ADC_PORT_INVERT_REG, val);
|
||||
@ -829,6 +887,7 @@ int setExternalSampling(int val) {
|
||||
int setReadoutMode(enum readoutMode mode) {
|
||||
analogEnable = 0;
|
||||
digitalEnable = 0;
|
||||
transceiverEnable = 0;
|
||||
switch (mode) {
|
||||
case ANALOG_ONLY:
|
||||
LOG(logINFO, ("Setting Analog Only Readout\n"));
|
||||
@ -843,6 +902,15 @@ int setReadoutMode(enum readoutMode mode) {
|
||||
analogEnable = 1;
|
||||
digitalEnable = 1;
|
||||
break;
|
||||
case TRANSCEIVER_ONLY:
|
||||
LOG(logINFO, ("Setting Transceiver Only Readout\n"));
|
||||
transceiverEnable = 1;
|
||||
break;
|
||||
case DIGITAL_AND_TRANSCEIVER:
|
||||
LOG(logINFO, ("Setting Digital & Transceiver Readout\n"));
|
||||
digitalEnable = 1;
|
||||
transceiverEnable = 1;
|
||||
break;
|
||||
default:
|
||||
LOG(logERROR, ("Cannot set unknown readout flag. 0x%x\n", mode));
|
||||
return FAIL;
|
||||
@ -850,66 +918,90 @@ int setReadoutMode(enum readoutMode mode) {
|
||||
|
||||
uint32_t addr = CONFIG_REG;
|
||||
uint32_t addr_readout_10g = READOUT_10G_ENABLE_REG;
|
||||
// default: analog only
|
||||
bus_w(addr, bus_r(addr) & (~CONFIG_DSBL_ANLG_OTPT_MSK) &
|
||||
(~CONFIG_ENBLE_DGTL_OTPT_MSK));
|
||||
|
||||
bus_w(addr, (bus_r(addr) | CONFIG_DSBL_ANLG_OTPT_MSK) &
|
||||
(~CONFIG_ENBLE_DGTL_OTPT_MSK) &
|
||||
(~CONFIG_ENBLE_TRNSCVR_OTPT_MSK));
|
||||
bus_w(addr_readout_10g, bus_r(addr_readout_10g) &
|
||||
(~READOUT_10G_ENABLE_ANLG_MSK) &
|
||||
~(READOUT_10G_ENABLE_DGTL_MSK));
|
||||
bus_w(addr_readout_10g,
|
||||
bus_r(addr_readout_10g) |
|
||||
((adcEnableMask_10g << READOUT_10G_ENABLE_ANLG_OFST) &
|
||||
READOUT_10G_ENABLE_ANLG_MSK));
|
||||
|
||||
// disable analog (digital only)
|
||||
if (!analogEnable) {
|
||||
bus_w(addr, bus_r(addr) | CONFIG_DSBL_ANLG_OTPT_MSK);
|
||||
~(READOUT_10G_ENABLE_DGTL_MSK) &
|
||||
~(READOUT_10G_ENABLE_TRNSCVR_MSK));
|
||||
if (analogEnable) {
|
||||
bus_w(addr, bus_r(addr) & ~(CONFIG_DSBL_ANLG_OTPT_MSK));
|
||||
bus_w(addr_readout_10g,
|
||||
bus_r(addr_readout_10g) & (~READOUT_10G_ENABLE_ANLG_MSK));
|
||||
bus_r(addr_readout_10g) |
|
||||
((adcEnableMask_10g << READOUT_10G_ENABLE_ANLG_OFST) &
|
||||
READOUT_10G_ENABLE_ANLG_MSK));
|
||||
}
|
||||
// enable digital (analog and digital)
|
||||
if (digitalEnable) {
|
||||
bus_w(addr, bus_r(addr) | CONFIG_ENBLE_DGTL_OTPT_MSK);
|
||||
bus_w(addr_readout_10g,
|
||||
bus_r(addr_readout_10g) | READOUT_10G_ENABLE_DGTL_MSK);
|
||||
}
|
||||
|
||||
// 1Gb
|
||||
if (!enableTenGigabitEthernet(-1)) {
|
||||
if (updateDatabytesandAllocateRAM() == FAIL) {
|
||||
return FAIL;
|
||||
}
|
||||
if (transceiverEnable) {
|
||||
bus_w(addr, bus_r(addr) | CONFIG_ENBLE_TRNSCVR_OTPT_MSK);
|
||||
bus_w(addr_readout_10g,
|
||||
bus_r(addr_readout_10g) |
|
||||
((transceiverMask << READOUT_10G_ENABLE_TRNSCVR_OFST) &
|
||||
READOUT_10G_ENABLE_TRNSCVR_MSK));
|
||||
}
|
||||
|
||||
// 10Gb
|
||||
else {
|
||||
// validate adcenablemask for 10g
|
||||
if (analogEnable &&
|
||||
adcEnableMask_10g != ((bus_r(READOUT_10G_ENABLE_REG) &
|
||||
READOUT_10G_ENABLE_ANLG_MSK) >>
|
||||
READOUT_10G_ENABLE_ANLG_OFST)) {
|
||||
LOG(logERROR, ("Setting readout mode failed. Could not set 10g adc "
|
||||
"enable mask to 0x%x\n.",
|
||||
adcEnableMask_10g));
|
||||
return FAIL;
|
||||
if (isControlServer) {
|
||||
// 1Gb
|
||||
if (!enableTenGigabitEthernet(-1)) {
|
||||
if (updateDatabytesandAllocateRAM() == FAIL) {
|
||||
return FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
// 10Gb
|
||||
else {
|
||||
// validate adcenablemask for 10g
|
||||
if (analogEnable &&
|
||||
adcEnableMask_10g != ((bus_r(READOUT_10G_ENABLE_REG) &
|
||||
READOUT_10G_ENABLE_ANLG_MSK) >>
|
||||
READOUT_10G_ENABLE_ANLG_OFST)) {
|
||||
LOG(logERROR,
|
||||
("Setting readout mode failed. Could not set 10g adc "
|
||||
"enable mask to 0x%x\n.",
|
||||
adcEnableMask_10g));
|
||||
return FAIL;
|
||||
}
|
||||
// validate transceivermask for 10g
|
||||
if (transceiverEnable &&
|
||||
transceiverMask != ((bus_r(READOUT_10G_ENABLE_REG) &
|
||||
READOUT_10G_ENABLE_TRNSCVR_MSK) >>
|
||||
READOUT_10G_ENABLE_TRNSCVR_OFST)) {
|
||||
LOG(logERROR, ("Setting readout mode failed. Could not set 10g "
|
||||
"transceiver enable mask to 0x%x\n.",
|
||||
transceiverMask));
|
||||
return FAIL;
|
||||
}
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int getReadoutMode() {
|
||||
if (analogEnable && digitalEnable) {
|
||||
if (analogEnable && digitalEnable && !transceiverEnable) {
|
||||
LOG(logDEBUG1, ("Getting readout: Analog & Digita\n"));
|
||||
return ANALOG_AND_DIGITAL;
|
||||
} else if (analogEnable && !digitalEnable) {
|
||||
} else if (analogEnable && !digitalEnable && !transceiverEnable) {
|
||||
LOG(logDEBUG1, ("Getting readout: Analog Only\n"));
|
||||
return ANALOG_ONLY;
|
||||
} else if (!analogEnable && digitalEnable) {
|
||||
} else if (!analogEnable && digitalEnable && !transceiverEnable) {
|
||||
LOG(logDEBUG1, ("Getting readout: Digital Only\n"));
|
||||
return DIGITAL_ONLY;
|
||||
} else if (!analogEnable && !digitalEnable && transceiverEnable) {
|
||||
LOG(logDEBUG1, ("Getting readout: Transceiver Only\n"));
|
||||
return TRANSCEIVER_ONLY;
|
||||
} else if (!analogEnable && digitalEnable && transceiverEnable) {
|
||||
LOG(logDEBUG1, ("Getting readout: Digital & Transceiver\n"));
|
||||
return DIGITAL_AND_TRANSCEIVER;
|
||||
} else {
|
||||
LOG(logERROR,
|
||||
("Read unknown readout (Both digital and analog are disabled)\n"));
|
||||
LOG(logERROR, ("Read unknown readout (analog enable:%d digital "
|
||||
"enable:%d transceiver enable:%d)\n",
|
||||
analogEnable, digitalEnable, transceiverEnable));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
@ -994,6 +1086,28 @@ int setNumDigitalSamples(int val) {
|
||||
|
||||
int getNumDigitalSamples() { return ndSamples; }
|
||||
|
||||
int setNumTransceiverSamples(int val) {
|
||||
if (val < 0) {
|
||||
LOG(logERROR, ("Invalid transceiver samples: %d\n", val));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("Setting number of transceiver samples %d\n", val));
|
||||
ntSamples = val;
|
||||
uint32_t addr = SAMPLES_TRANSCEIVER_REG;
|
||||
bus_w(addr, bus_r(addr) & ~SAMPLES_TRANSCEIVER_MSK);
|
||||
bus_w(addr, bus_r(addr) | ((val << SAMPLES_TRANSCEIVER_OFST) &
|
||||
SAMPLES_TRANSCEIVER_MSK));
|
||||
// 1Gb
|
||||
if (!enableTenGigabitEthernet(-1)) {
|
||||
if (updateDatabytesandAllocateRAM() == FAIL) {
|
||||
return FAIL;
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int getNumTransceiverSamples() { return ntSamples; }
|
||||
|
||||
int setExpTime(int64_t val) {
|
||||
if (val < 0) {
|
||||
LOG(logERROR, ("Invalid exptime: %lld ns\n", (long long int)val));
|
||||
@ -2098,6 +2212,7 @@ int startStateMachine() {
|
||||
LOG(logINFOGREEN, ("Virtual Acquisition started\n"));
|
||||
return OK;
|
||||
#endif
|
||||
|
||||
int send_to_10g = enableTenGigabitEthernet(-1);
|
||||
// 1 giga udp
|
||||
if (send_to_10g == 0) {
|
||||
@ -2124,6 +2239,38 @@ int startStateMachine() {
|
||||
~CONTROL_STRT_EXPSR_MSK);
|
||||
|
||||
LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
|
||||
|
||||
// TODO: Temporary Matternhorn Specific ( will be moved to the pattern )
|
||||
if (transceiverEnable) {
|
||||
uint32_t addr = 0x202 << MEM_MAP_SHIFT;
|
||||
bus_w(addr, bus_r(addr) | (1 << 1));
|
||||
LOG(logINFOBLUE, ("Writing 1 to reg 0x202\n"))
|
||||
usleep(1);
|
||||
cleanFifos();
|
||||
usleep(1);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
int startReadOut() {
|
||||
LOG(logINFOBLUE, ("Starting Readout\n"));
|
||||
#ifdef VIRTUAL
|
||||
return startStateMachine();
|
||||
#endif
|
||||
int send_to_10g = enableTenGigabitEthernet(-1);
|
||||
// 1 giga udp
|
||||
if (send_to_10g == 0) {
|
||||
// create udp socket
|
||||
if (createUDPSocket(0) != OK) {
|
||||
return FAIL;
|
||||
}
|
||||
// update header with modId, detType and version. Reset offset and fnum
|
||||
createUDPPacketHeader(udpPacketData, getHardwareSerialNumber());
|
||||
}
|
||||
|
||||
cleanFifos();
|
||||
usleep(1);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -2188,6 +2335,7 @@ void *start_timer(void *arg) {
|
||||
srcOffset += dataSize;
|
||||
|
||||
sendUDPPacket(0, 0, packetData, packetSize);
|
||||
// LOG(logINFOBLUE, ("packetsize:%d\n", packetSize));
|
||||
}
|
||||
LOG(logINFO, ("Sent frame: %d [%lld]\n", iframes, frameNr + iframes));
|
||||
clock_gettime(CLOCK_REALTIME, &end);
|
||||
@ -2236,6 +2384,7 @@ int stopStateMachine() {
|
||||
}
|
||||
|
||||
enum runStatus getRunStatus() {
|
||||
|
||||
LOG(logDEBUG1, ("Getting status\n"));
|
||||
// scan error or running
|
||||
if (sharedMemory_getScanStatus() == ERROR) {
|
||||
@ -2291,6 +2440,7 @@ enum runStatus getRunStatus() {
|
||||
|
||||
// 1g might still be transmitting or reading from fifo (not virtual)
|
||||
if (!enableTenGigabitEthernet(-1) && checkDataInFifo()) {
|
||||
LOG(logINFOBLUE, ("Status: Transmitting (Data in Fifo)\n"));
|
||||
return TRANSMITTING;
|
||||
}
|
||||
|
||||
@ -2345,25 +2495,20 @@ void waitForAcquisitionEnd() {
|
||||
|
||||
void unsetFifoReadStrobes() {
|
||||
bus_w(DUMMY_REG, bus_r(DUMMY_REG) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK) &
|
||||
(~DUMMY_DGTL_FIFO_RD_STRBE_MSK));
|
||||
(~DUMMY_DGTL_FIFO_RD_STRBE_MSK) &
|
||||
(~DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK));
|
||||
}
|
||||
|
||||
void readSample(int ns) {
|
||||
int readSample(int ns) {
|
||||
int sampleRead = 0;
|
||||
uint32_t addr = DUMMY_REG;
|
||||
LOG(logDEBUG1, ("sample :%d\n", ns));
|
||||
|
||||
// read adcs
|
||||
if (analogEnable && ns < naSamples) {
|
||||
|
||||
uint32_t fifoAddr = FIFO_DATA_REG;
|
||||
|
||||
// read strobe to all analog fifos
|
||||
bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK);
|
||||
bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
|
||||
|
||||
// wait for 1 us to latch different clocks of read and read strobe
|
||||
for (int i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
|
||||
;
|
||||
|
||||
if (!(ns % 1000)) {
|
||||
LOG(logDEBUG1, ("Reading sample ns:%d of %d AEmtpy:0x%x AFull:0x%x "
|
||||
"Status:0x%x\n",
|
||||
@ -2384,6 +2529,11 @@ void readSample(int ns) {
|
||||
bus_w(addr, bus_r(addr) | ((ich << DUMMY_FIFO_CHNNL_SLCT_OFST) &
|
||||
DUMMY_FIFO_CHNNL_SLCT_MSK));
|
||||
|
||||
// wait for 1 us to latch different clocks of read and read
|
||||
// strobe
|
||||
for (int i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
|
||||
;
|
||||
|
||||
// read fifo and write it to current position of data pointer
|
||||
*((uint16_t *)analogDataPtr) = bus_r16(fifoAddr);
|
||||
|
||||
@ -2395,21 +2545,22 @@ void readSample(int ns) {
|
||||
|
||||
// increment pointer to data out destination
|
||||
analogDataPtr += 2;
|
||||
sampleRead = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// read digital output
|
||||
if (digitalEnable && ns < ndSamples) {
|
||||
// read strobe to digital fifo
|
||||
bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK);
|
||||
bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK));
|
||||
// read strobe to all analog fifos
|
||||
bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK);
|
||||
bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
|
||||
|
||||
// wait for 1 us to latch different clocks of read and read strobe
|
||||
for (int i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
|
||||
;
|
||||
}
|
||||
|
||||
// read digital output
|
||||
if (digitalEnable && ns < ndSamples) {
|
||||
|
||||
// wait as it is connected directly to fifo running on a different clock
|
||||
if (!(ns % 1000)) {
|
||||
LOG(logDEBUG1,
|
||||
("Reading sample ns:%d of %d DEmtpy:%d DFull:%d Status:0x%x\n",
|
||||
@ -2427,37 +2578,127 @@ void readSample(int ns) {
|
||||
*((uint64_t *)digitalDataPtr) =
|
||||
get64BitReg(FIFO_DIN_LSB_REG, FIFO_DIN_MSB_REG);
|
||||
digitalDataPtr += 8;
|
||||
sampleRead = 1;
|
||||
|
||||
// read strobe to digital fifo
|
||||
bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK);
|
||||
bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK));
|
||||
|
||||
// wait for 1 us to latch different clocks of read and read strobe
|
||||
for (int i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
|
||||
;
|
||||
}
|
||||
|
||||
// read transceivers
|
||||
if (transceiverEnable && ns < ntSamples) {
|
||||
uint32_t tStatusAddr = FIFO_TIN_STATUS_REG;
|
||||
|
||||
if (!(ns % 1000)) {
|
||||
LOG(logDEBUG1,
|
||||
("Reading sample ns:%d of %d TReg:0x%x Status:0x%x\n", ns,
|
||||
ntSamples, bus_r(tStatusAddr), bus_r(STATUS_REG)));
|
||||
}
|
||||
|
||||
// loop through all channels
|
||||
for (int ich = 0; ich < NCHAN_TRANSCEIVER; ++ich) {
|
||||
|
||||
// if channel is in enable mask
|
||||
if ((1 << ich) & (transceiverMask)) {
|
||||
|
||||
int offset = FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST + ich;
|
||||
uint32_t mask = (1 << offset);
|
||||
// int empty = ((bus_r(tStatusAddr) & mask) >> offset);
|
||||
|
||||
// if fifo not empty
|
||||
// if (!empty) {
|
||||
LOG(logDEBUG1,
|
||||
("ns:%d Transceiver Fifo %d NOT Empty\n", ns, ich));
|
||||
|
||||
// unselect channel
|
||||
bus_w(addr, bus_r(addr) & ~(DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_MSK));
|
||||
|
||||
// select channel
|
||||
bus_w(addr, bus_r(addr) |
|
||||
((ich << DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_OFST) &
|
||||
DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_MSK));
|
||||
|
||||
// wait for 1 us to latch different clocks of read and read
|
||||
// strobe
|
||||
for (int i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
|
||||
;
|
||||
|
||||
// read fifo and write it to current position of data
|
||||
// pointer
|
||||
*((uint64_t *)transceiverDataPtr) =
|
||||
get64BitReg(FIFO_TIN_LSB_REG, FIFO_TIN_MSB_REG);
|
||||
transceiverDataPtr += 8;
|
||||
sampleRead = 1;
|
||||
//}
|
||||
}
|
||||
}
|
||||
|
||||
// read strobe
|
||||
bus_w(addr, bus_r(addr) | DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK);
|
||||
usleep(5 * 1000);
|
||||
bus_w(addr, bus_r(addr) & (~DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK));
|
||||
|
||||
// wait for 1 us to latch different clocks of read and read
|
||||
// strobe
|
||||
for (int i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
|
||||
;
|
||||
}
|
||||
|
||||
LOG(logDEBUG1, ("sample read:%d\n", sampleRead));
|
||||
return sampleRead;
|
||||
}
|
||||
|
||||
uint32_t checkDataInFifo() {
|
||||
uint32_t dataPresent = 0;
|
||||
if (analogEnable) {
|
||||
uint32_t analogFifoEmpty = bus_r(FIFO_EMPTY_REG);
|
||||
uint32_t fifoEmtpy = bus_r(FIFO_EMPTY_REG);
|
||||
LOG(logDEBUG1,
|
||||
("Analog Fifo Empty (32 channels): 0x%08x\n", analogFifoEmpty));
|
||||
dataPresent = (~analogFifoEmpty);
|
||||
("Analog Fifo Empty (32 channels): 0x%08x\n", fifoEmtpy));
|
||||
dataPresent = (~fifoEmtpy);
|
||||
}
|
||||
if (!dataPresent && digitalEnable) {
|
||||
int digitalFifoEmpty =
|
||||
int fifoEmtpy =
|
||||
((bus_r(FIFO_DIN_STATUS_REG) & FIFO_DIN_STATUS_FIFO_EMPTY_MSK) >>
|
||||
FIFO_DIN_STATUS_FIFO_EMPTY_OFST);
|
||||
LOG(logINFO, ("Digital Fifo Empty: %d\n", digitalFifoEmpty));
|
||||
dataPresent = (digitalFifoEmpty ? 0 : 1);
|
||||
LOG(logDEBUG1, ("Digital Fifo Empty: %d\n", fifoEmtpy));
|
||||
dataPresent = (fifoEmtpy ? 0 : 1);
|
||||
}
|
||||
LOG(logDEBUG2, ("Data in Fifo :0x%x\n", dataPresent));
|
||||
if (!dataPresent && transceiverEnable) {
|
||||
int fifoEmtpy = 1;
|
||||
for (int ich = 0; ich != 4; ++ich) {
|
||||
if ((1 << ich) & (transceiverMask)) {
|
||||
uint32_t mask = FIFO_TIN_STATUS_FIFO_EMPTY_1_MSK << ich;
|
||||
int offset = FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST + ich;
|
||||
int iFifoEmpty =
|
||||
((bus_r(FIFO_TIN_STATUS_REG) & mask) >> offset);
|
||||
if (iFifoEmpty == 0) {
|
||||
fifoEmtpy = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
LOG(logDEBUG1, ("Transceiver Fifo Empty: %d reg:0x%x\n", fifoEmtpy,
|
||||
bus_r(FIFO_TIN_STATUS_REG)));
|
||||
dataPresent = (fifoEmtpy ? 0 : 1);
|
||||
}
|
||||
LOG(logDEBUG1, ("Data in Fifo :0x%x\n", dataPresent));
|
||||
return dataPresent;
|
||||
}
|
||||
|
||||
// only called for starting of a new frame
|
||||
int checkFifoForEndOfAcquisition() {
|
||||
LOG(logDEBUG1, ("Check for end of acq\n"));
|
||||
uint32_t dataPresent = checkDataInFifo();
|
||||
LOG(logDEBUG2, ("status:0x%x\n", bus_r(STATUS_REG)));
|
||||
LOG(logDEBUG1, ("dataPresent:%d\n", dataPresent));
|
||||
|
||||
// as long as no data
|
||||
while (!dataPresent) {
|
||||
// acquisition done
|
||||
if (!runBusy()) {
|
||||
LOG(logDEBUG1, ("Not running\n"));
|
||||
// wait to be sure there is no data in fifo
|
||||
usleep(WAIT_TME_US_FR_ACQDONE_REG);
|
||||
|
||||
@ -2484,18 +2725,35 @@ int readFrameFromFifo() {
|
||||
int ns = 0;
|
||||
// point the data pointer to the starting position of data
|
||||
analogDataPtr = analogData;
|
||||
memset(analogData, 0, analogDataBytes);
|
||||
digitalDataPtr = digitalData;
|
||||
memset(digitalData, 0, digitalDataBytes);
|
||||
transceiverDataPtr = transceiverData;
|
||||
memset(transceiverData, 0, transceiverDataBytes);
|
||||
|
||||
// no data for this frame
|
||||
/*if (!checkDataInFifo()) {
|
||||
return FAIL;
|
||||
}*/
|
||||
// for startacquistiion
|
||||
if (checkFifoForEndOfAcquisition() == FAIL) {
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
// read Sample
|
||||
int maxSamples = (naSamples > ndSamples) ? naSamples : ndSamples;
|
||||
int maxSamples = 0;
|
||||
if (analogEnable && naSamples > maxSamples)
|
||||
maxSamples = naSamples;
|
||||
if (digitalEnable && ndSamples > maxSamples)
|
||||
maxSamples = ndSamples;
|
||||
if (transceiverEnable && ntSamples > maxSamples)
|
||||
maxSamples = ntSamples;
|
||||
while (ns < maxSamples) {
|
||||
// chceck if no data in fifo, return ns?//FIXME: ask Anna
|
||||
readSample(ns);
|
||||
if (!readSample(ns)) {
|
||||
LOG(logWARNING, ("No more samples to read\n"));
|
||||
return OK;
|
||||
}
|
||||
ns++;
|
||||
}
|
||||
|
||||
@ -2523,8 +2781,7 @@ int getTotalNumberOfChannels() {
|
||||
}
|
||||
|
||||
void getNumberOfChannels(int *nchanx, int *nchany) {
|
||||
int nachans = 0, ndchans = 0;
|
||||
// analog channels (normal, analog/digital readout)
|
||||
int nachans = 0, ndchans = 0, ntchans = 0;
|
||||
if (analogEnable) {
|
||||
uint32_t mask =
|
||||
enableTenGigabitEthernet(-1) ? adcEnableMask_10g : adcEnableMask_1g;
|
||||
@ -2539,12 +2796,19 @@ void getNumberOfChannels(int *nchanx, int *nchany) {
|
||||
LOG(logDEBUG1, ("Analog Channels: %d\n", nachans));
|
||||
}
|
||||
|
||||
// digital channels (digital, analog/digital readout)
|
||||
if (digitalEnable) {
|
||||
ndchans = 64;
|
||||
LOG(logDEBUG, ("Digital Channels: %d\n", ndchans));
|
||||
}
|
||||
*nchanx = nachans + ndchans;
|
||||
if (transceiverEnable) {
|
||||
for (int ich = 0; ich < NCHAN_TRANSCEIVER; ++ich) {
|
||||
if ((transceiverMask & (1 << ich)) != 0U)
|
||||
++ntchans;
|
||||
}
|
||||
|
||||
LOG(logDEBUG1, ("Transceiver Channels: %d\n", ntchans));
|
||||
}
|
||||
*nchanx = nachans + ndchans + ntchans;
|
||||
LOG(logDEBUG, ("Total #Channels: %d\n", *nchanx));
|
||||
*nchany = 1;
|
||||
}
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
#include "sls/sls_detector_defs.h"
|
||||
|
||||
#define MIN_REQRD_VRSN_T_RD_API 0x181130
|
||||
#define REQRD_FRMWR_VRSN 0x230403
|
||||
#define REQRD_FRMWR_VRSN 0x230705
|
||||
|
||||
#define NUM_HARDWARE_VERSIONS (1)
|
||||
#define HARDWARE_VERSION_NUMBERS \
|
||||
@ -18,9 +18,11 @@
|
||||
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NCHAN (36)
|
||||
#define NCHAN (40)
|
||||
#define NCHAN_ANALOG (32)
|
||||
#define NCHAN_DIGITAL (64)
|
||||
#define NCHAN_TRANSCEIVER (4)
|
||||
#define NBITS_PER_TRANSCEIVER (64)
|
||||
#define NCHIP (1)
|
||||
#define NDAC (24)
|
||||
#define NPWR (6)
|
||||
@ -52,6 +54,8 @@
|
||||
#define DEFAULT_ADC_CLK (40) // 20
|
||||
#define DEFAULT_SYNC_CLK (40) // 20
|
||||
#define DEFAULT_DBIT_CLK (200)
|
||||
#define DEFAULT_TRANSCEIVER_MASK (0x3)
|
||||
#define MAX_TRANSCEIVER_MASK (0xF)
|
||||
|
||||
#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user