updated ctb and moench, moench not tested

This commit is contained in:
2019-03-05 09:38:10 +01:00
parent 08bd2378f4
commit c56561bc9f
17 changed files with 433 additions and 224 deletions

View File

@ -85,8 +85,8 @@
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//0xCACA#define FIFO_DATA_WRD_OFST (16)
//0xCACA#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
/* FIFO Status RO register TODO */
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)

View File

@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: ebee9e308e98f518775d42685602febda9b763ea
Revision: 29
Repsitory UUID: 08bd2378f4956ea9a0b75381872854b3b129288f
Revision: 32
Branch: refactor
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4365
Last Changed Date: 2019-03-01 08:13:34.000000002 +0100 ./RegisterDefs.h
Last Changed Rev: 4372
Last Changed Date: 2019-03-04 17:47:37.000000002 +0100 ./RegisterDefs.h

View File

@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "ebee9e308e98f518775d42685602febda9b763ea"
#define GITREPUUID "08bd2378f4956ea9a0b75381872854b3b129288f"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4365
#define GITDATE 0x20190301
#define GITREV 0x4372
#define GITDATE 0x20190304
#define GITBRANCH "refactor"

View File

@ -103,7 +103,7 @@ void basictests() {
FILE_LOG(logERROR, ("%s\n\n", firmware_message));
firmware_compatibility = FAIL;
firmware_check_done = 1;
cprintf(RED,"exiting for now!\n");exit(-1); return;
return;
}
uint16_t hversion = getHardwareVersionNumber();
@ -204,7 +204,7 @@ int checkType() {
return OK;
}
uint32_t testFpga(void) {
int testFpga() {
#ifdef VIRTUAL
return OK;
#endif
@ -538,6 +538,9 @@ void setupDetector() {
cleanFifos(); // FIXME: why twice?
resetCore();
// 1G UDP
enableTenGigabitEthernet(0);
//Initialization of acquistion parameters
setTimer(SAMPLES, DEFAULT_NUM_SAMPLES); // update databytes and allocate ram
setTimer(FRAME_NUMBER, DEFAULT_NUM_FRAMES);
@ -545,9 +548,8 @@ void setupDetector() {
setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY);
setTiming(DEFAULT_TIMING_MODE);
setReadOutFlags(NORMAL_READOUT);
// 1G UDP
enableTenGigabitEthernet(0);
// clear roi
{
int ret = OK, retvalsize = 0;
@ -953,7 +955,6 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
}
retval = nSamples;
FILE_LOG(logINFO, ("\tGetting #samples: %lld\n", (long long int)retval));
break;
default:
@ -1031,6 +1032,7 @@ int validateTimer(enum timerIndex ind, int64_t val, int64_t retval) {
val = (val) / (1E-3 * ADC_CLK);
if (val != retval)
return FAIL;
break;
default:
break;
}
@ -1614,7 +1616,7 @@ int enableTenGigabitEthernet(int val) {
/* ctb specific - pll, flashing fpga */
/* ctb specific - configure frequency, phase, pll */
// ind can only be ADC_CLK or DBIT_CLK
@ -1739,6 +1741,9 @@ int getAdcOffsetRegister(int adc) {
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_DBT_PPLN_MSK) >> ADC_OFFSET_DBT_PPLN_OFST);
}
// patterns
uint64_t writePatternIOControl(uint64_t word) {
if (word != -1) {
FILE_LOG(logINFO, ("Setting Pattern - I/O Control: 0x%llx\n", (long long int) word));
@ -2176,10 +2181,12 @@ enum runStatus getRunStatus(){
return TRANSMITTING;
}
/*if (retval & STATUS_ALL_FF_EMPTY_MSK) {
FILE_LOG(logINFOBLUE, ("Status: Transmitting (All fifo empty)\n"));
return TRANSMITTING;
}*/
if (digitalEnable && !analogEnable) {
if (retval & STATUS_ALL_FF_EMPTY_MSK) {
FILE_LOG(logINFOBLUE, ("Status: Transmitting (All fifo empty)\n"));
return TRANSMITTING;
}
}
if (! (retval & STATUS_IDLE_MSK)) {
FILE_LOG(logINFOBLUE, ("Status: Idle\n"));