added gated clk for another pll for ctb

python/slsdet/detector.py

@@ -2833,6 +2833,16 @@ class Detector(CppDetectorApi):
     def runclk(self, freq):
         ut.set_using_dict(self.setRUNClock, freq)
 
+    @property
+    @element
+    def gatedclk(self):
+        """[Ctb][Moench] Run clock in MHz."""
+        return self.getGatedClock()
+
+    @gatedclk.setter
+    def gatedclk(self, freq):
+        ut.set_using_dict(self.setGatedClock, freq)
+
     @property
     @element
     def romode(self):

slsDetectorServers/CMakeLists.txt

@@ -11,9 +11,9 @@ install(TARGETS slsProjectCSettings
     PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}
 )
 add_subdirectory(ctbDetectorServer)
-add_subdirectory(eigerDetectorServer)
+#add_subdirectory(eigerDetectorServer)
-add_subdirectory(gotthardDetectorServer)
+#add_subdirectory(gotthardDetectorServer)
-add_subdirectory(jungfrauDetectorServer)
+#add_subdirectory(jungfrauDetectorServer)
-add_subdirectory(mythen3DetectorServer)
+#add_subdirectory(mythen3DetectorServer)
-add_subdirectory(gotthard2DetectorServer)
+#add_subdirectory(gotthard2DetectorServer)
-add_subdirectory(moenchDetectorServer)
+#add_subdirectory(moenchDetectorServer)

slsDetectorServers/ctbDetectorServer/RegisterDefs.h

@@ -380,6 +380,22 @@
 #define PLL_CNTRL_ADDR_OFST     (16)
 #define PLL_CNTRL_ADDR_MSK      (0x0000003F << PLL_CNTRL_ADDR_OFST)
 
+/* Reconfiguratble PLL Paramater RW register */
+#define PLL_A_PARAM_REG (0x93 << MEM_MAP_SHIFT)
+
+/* Reconfiguratble PLL Control RW regiser */
+#define PLL_A_CNTRL_REG (0x94 << MEM_MAP_SHIFT)
+
+#define PLL_A_CNTRL_RCNFG_PRMTR_RST_OFST (0)
+#define PLL_A_CNTRL_RCNFG_PRMTR_RST_MSK                                        \
+    (0x00000001 << PLL_A_CNTRL_RCNFG_PRMTR_RST_OFST)
+#define PLL_A_CNTRL_WR_PRMTR_OFST (2)
+#define PLL_A_CNTRL_WR_PRMTR_MSK  (0x00000001 << PLL_A_CNTRL_WR_PRMTR_OFST)
+#define PLL_A_CNTRL_PLL_RST_OFST  (3)
+#define PLL_A_CNTRL_PLL_RST_MSK   (0x00000001 << PLL_A_CNTRL_PLL_RST_OFST)
+#define PLL_A_CNTRL_ADDR_OFST     (16)
+#define PLL_A_CNTRL_ADDR_MSK      (0x0000003F << PLL_A_CNTRL_ADDR_OFST)
+
 /* Pattern Control RW register */
 #define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
 

slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c

@@ -62,7 +62,7 @@ uint32_t adcEnableMask_1g = BIT32_MSK;
 uint8_t adcEnableMask_10g = 0xFF;
 
 int32_t clkPhase[NUM_CLOCKS] = {};
-uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200};
+uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200, 400};
 int dacValues[NDAC] = {};
 // software limit that depends on the current chip on the ctb
 int vLimit = 0;
@@ -471,6 +471,7 @@ void setupDetector() {
         clkFrequency[ADC_CLK] = DEFAULT_ADC_CLK;
         clkFrequency[SYNC_CLK] = DEFAULT_SYNC_CLK;
         clkFrequency[DBIT_CLK] = DEFAULT_DBIT_CLK;
+        clkFrequency[GATED_CLK] = DEFAULT_GATED_CLK;
         for (int i = 0; i < NDAC; ++i)
             dacValues[i] = -1;
     }
@@ -488,7 +489,15 @@ void setupDetector() {
 #endif
     setupUDPCommParameters();
 
-    ALTERA_PLL_ResetPLLAndReconfiguration();
+    // altera pll
+    ALTERA_PLL_SetDefines(
+        PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK,
+        PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
+        PLL_CNTRL_ADDR_OFST, PLL_A_CNTRL_REG, PLL_A_PARAM_REG);
+    // both plls
+    ALTERA_PLL_ResetPLLAndReconfiguration(0);
+    ALTERA_PLL_ResetPLLAndReconfiguration(1);
+
     resetCore();
     resetPeripheral();
     cleanFifos();
@@ -548,12 +557,6 @@ void setupDetector() {
     INA226_CalibrateCurrentRegister(I2C_POWER_VD_DEVICE_ID);
     setVchip(VCHIP_MIN_MV);
 
-    // altera pll
-    ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG,
-                          PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK,
-                          PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
-                          PLL_CNTRL_ADDR_OFST);
-
     setADCInvertRegister(0); // depends on chip
 
     LOG(logINFOBLUE, ("Setting Default parameters\n"));
@@ -1784,19 +1787,29 @@ int setFrequency(enum CLKINDEX ind, int val) {
         return FAIL;
     }
 
+    int pllIndex = 0;
+    int vcofreq = PLL_VCO_FREQ_MHZ;
+    if (ind == GATED_CLK) {
+        pllIndex = 1;
+        vcofreq = PLL_A_VCO_FREQ_MHZ;
+    }
     // Remembering adcphase/ dbit phase in degrees
-    int adcPhase = getPhase(ADC_CLK, 1);
+    int adcPhase = 0, dbitPhase = 0;
+    if (pllIndex == 0) {
+        adcPhase = getPhase(ADC_CLK, 1);
         LOG(logDEBUG1, ("\tRemembering ADC phase: %d degrees\n", adcPhase));
-    int dbitPhase = getPhase(DBIT_CLK, 1);
+        dbitPhase = getPhase(DBIT_CLK, 1);
         LOG(logDEBUG1, ("\tRemembering DBIT phase: %d degrees\n", dbitPhase));
+    }
 
     // Calculate and set output frequency
     clkFrequency[ind] =
-        ALTERA_PLL_SetOuputFrequency(ind, PLL_VCO_FREQ_MHZ, val);
+        ALTERA_PLL_SetOuputFrequency(pllIndex, ind, vcofreq, val);
     LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind],
                   ind, clkFrequency[ind]));
 
     // phase reset by pll (when setting output frequency)
+    if (pllIndex == 0) {
         clkPhase[ADC_CLK] = 0;
         clkPhase[DBIT_CLK] = 0;
 
@@ -1813,6 +1826,7 @@ int setFrequency(enum CLKINDEX ind, int val) {
         if (ind != SYNC_CLK) {
             configureSyncFrequency(ind);
         }
+    }
     return OK;
 }
 

slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h

@@ -86,8 +86,8 @@ enum DACINDEX {
     D_PWR_A,
     D_PWR_IO
 };
-enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
+enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, GATED_CLK, NUM_CLOCKS };
-#define CLK_NAMES "run", "adc", "sync", "dbit"
+#define CLK_NAMES "run", "adc", "sync", "dbit", "gated"
 
 /* Hardware Definitions */
 #define NCHAN                   (36)
@@ -124,6 +124,7 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
 #define DEFAULT_ADC_CLK               (40)  // 20
 #define DEFAULT_SYNC_CLK              (40)  // 20
 #define DEFAULT_DBIT_CLK              (200)
+#define DEFAULT_GATED_CLK             (400)
 
 #define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
 
@@ -162,3 +163,4 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
 
 #define MAXIMUM_ADC_CLK    (65)
 #define PLL_VCO_FREQ_MHZ   (800)
+#define PLL_A_VCO_FREQ_MHZ (400)

slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h

@@ -33,18 +33,18 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
  */
 void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
                            uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
-                           int aofst);
+                           int aofst, uint32_t acreg, uint32_t apreg);
 #endif
 
 /**
  * Reset only PLL
  */
-void ALTERA_PLL_ResetPLL();
+void ALTERA_PLL_ResetPLL(int pllIndex);
 
 /**
  * Reset PLL Reconfiguration and PLL
  */
-void ALTERA_PLL_ResetPLLAndReconfiguration();
+void ALTERA_PLL_ResetPLLAndReconfiguration(int pllIndex);
 
 /**
  * Set PLL Reconfig register
@@ -53,7 +53,7 @@ void ALTERA_PLL_ResetPLLAndReconfiguration();
  * @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR
  * mask)
  */
-void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
+void ALTERA_PLL_SetPllReconfigReg(int pllIndex, uint32_t reg, uint32_t val,
                                   int useSecondWRMask);
 
 /**
@@ -75,4 +75,5 @@ void ALTERA_PLL_SetModePolling();
  * @param value frequency to set to
  * @param frequency set
  */
-int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value);
+int ALTERA_PLL_SetOuputFrequency(int pllIndex, int clkIndex, int pllVCOFreqMhz,
+                                 int value);

slsDetectorServers/slsDetectorServer/src/ALTERA_PLL.c

@@ -135,6 +135,8 @@ int ALTERA_PLL_Cntrl_DBIT_ClkIndex = 0;
 uint32_t ALTERA_PLL_Cntrl_PLLRstMask = 0x0;
 uint32_t ALTERA_PLL_Cntrl_AddrMask = 0x0;
 int ALTERA_PLL_Cntrl_AddrOfst = 0;
+uint32_t ALTERA_PLL_A_Cntrl_Reg = 0x0;
+uint32_t ALTERA_PLL_A_Param_Reg = 0x0;
 
 #ifdef JUNGFRAUD
 void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
@@ -153,7 +155,7 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
 #else
 void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
                            uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
-                           int aofst) {
+                           int aofst, uint32_t acreg, uint32_t apreg) {
     ALTERA_PLL_Cntrl_Reg = creg;
     ALTERA_PLL_Param_Reg = preg;
     ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
@@ -161,44 +163,55 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
     ALTERA_PLL_Cntrl_PLLRstMask = prmsk;
     ALTERA_PLL_Cntrl_AddrMask = amsk;
     ALTERA_PLL_Cntrl_AddrOfst = aofst;
+    ALTERA_PLL_A_Cntrl_Reg = acreg;
+    ALTERA_PLL_A_Param_Reg = apreg;
 }
 #endif
 
-void ALTERA_PLL_ResetPLL() {
+void ALTERA_PLL_ResetPLL(int pllIndex) {
-    LOG(logINFO, ("Resetting only PLL\n"));
+    LOG(logINFO, ("Resetting only PLL %d\n", pllIndex));
+    uint32_t cntrlReg = ALTERA_PLL_Cntrl_Reg;
+    if (pllIndex == 1) {
+        cntrlReg = ALTERA_PLL_A_Cntrl_Reg;
+    }
 
     LOG(logDEBUG2, ("pllrstmsk:0x%x\n", ALTERA_PLL_Cntrl_PLLRstMask));
 
-    bus_w(ALTERA_PLL_Cntrl_Reg,
+    bus_w(cntrlReg, bus_r(cntrlReg) | ALTERA_PLL_Cntrl_PLLRstMask);
-          bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
+    LOG(logDEBUG2, ("Set PLL Reset mSk: cntrlReg:0x%x\n", bus_r(cntrlReg)));
-    LOG(logDEBUG2, ("Set PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
-                    bus_r(ALTERA_PLL_Cntrl_Reg)));
 
     usleep(ALTERA_PLL_WAIT_TIME_US);
 
-    bus_w(ALTERA_PLL_Cntrl_Reg,
+    bus_w(cntrlReg, bus_r(cntrlReg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
-          bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
+    LOG(logDEBUG2, ("UnSet PLL Reset mSk: cntrlReg:0x%x\n", bus_r(cntrlReg)));
-    LOG(logDEBUG2, ("UnSet PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
-                    bus_r(ALTERA_PLL_Cntrl_Reg)));
 }
 
-void ALTERA_PLL_ResetPLLAndReconfiguration() {
+void ALTERA_PLL_ResetPLLAndReconfiguration(int pllIndex) {
-    LOG(logINFO, ("Resetting PLL and Reconfiguration\n"));
+    LOG(logINFO, ("Resetting PLL and Reconfiguration of pll %d\n", pllIndex));
+    uint32_t cntrlReg = ALTERA_PLL_Cntrl_Reg;
+    if (pllIndex == 1) {
+        cntrlReg = ALTERA_PLL_A_Cntrl_Reg;
+    }
 
-    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) |
+    bus_w(cntrlReg, bus_r(cntrlReg) | ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask |
-                                    ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask |
                         ALTERA_PLL_Cntrl_PLLRstMask);
     usleep(ALTERA_PLL_WAIT_TIME_US);
-    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) &
+    bus_w(cntrlReg, bus_r(cntrlReg) & ~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask &
-                                    ~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask &
                         ~ALTERA_PLL_Cntrl_PLLRstMask);
 }
 
-void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
+void ALTERA_PLL_SetPllReconfigReg(int pllIndex, uint32_t reg, uint32_t val,
                                   int useSecondWRMask) {
-    LOG(logDEBUG1,
+    LOG(logDEBUG1, ("Setting PLL %d Reconfig Reg, reg:0x%x, val:0x%x, "
-        ("Setting PLL Reconfig Reg, reg:0x%x, val:0x%x, useSecondWRMask:%d)\n",
+                    "useSecondWRMask:%d)\n",
-         reg, val, useSecondWRMask));
+                    pllIndex, reg, val, useSecondWRMask));
+
+    uint32_t cntrlReg = ALTERA_PLL_Cntrl_Reg;
+    uint32_t paramReg = ALTERA_PLL_Param_Reg;
+    if (pllIndex == 1) {
+        cntrlReg = ALTERA_PLL_A_Cntrl_Reg;
+        paramReg = ALTERA_PLL_A_Param_Reg;
+    }
 
     uint32_t wrmask = ALTERA_PLL_Cntrl_WrPrmtrMask;
 #ifdef JUNGFRAUD
@@ -210,38 +223,34 @@ void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
     LOG(logDEBUG2,
         ("pllparamreg:0x%x pllcontrolreg:0x%x addrofst:%d addrmsk:0x%x "
          "wrmask:0x%x\n",
-         ALTERA_PLL_Param_Reg, ALTERA_PLL_Cntrl_Reg, ALTERA_PLL_Cntrl_AddrOfst,
+         paramReg, cntrlReg, ALTERA_PLL_Cntrl_AddrOfst,
          ALTERA_PLL_Cntrl_AddrMask, wrmask));
 
     // set parameter
-    bus_w(ALTERA_PLL_Param_Reg, val);
+    bus_w(paramReg, val);
-    LOG(logDEBUG2, ("Set Parameter: ALTERA_PLL_Param_Reg:0x%x\n",
+    LOG(logDEBUG2, ("Set Parameter: paramReg:0x%x\n", bus_r(paramReg)));
-                    bus_r(ALTERA_PLL_Param_Reg)));
     usleep(ALTERA_PLL_WAIT_TIME_US);
 
     // set address
-    bus_w(ALTERA_PLL_Cntrl_Reg,
+    bus_w(cntrlReg,
           (reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask);
-    LOG(logDEBUG2, ("Set Address: ALTERA_PLL_Cntrl_Reg:0x%x\n",
+    LOG(logDEBUG2, ("Set Address: cntrlReg:0x%x\n", bus_r(cntrlReg)));
-                    bus_r(ALTERA_PLL_Cntrl_Reg)));
     usleep(ALTERA_PLL_WAIT_TIME_US);
 
     // write parameter
-    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | wrmask);
+    bus_w(cntrlReg, bus_r(cntrlReg) | wrmask);
-    LOG(logDEBUG2, ("Set WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
+    LOG(logDEBUG2, ("Set WR bit: cntrlReg:0x%x\n", bus_r(cntrlReg)));
-                    bus_r(ALTERA_PLL_Cntrl_Reg)));
 
     usleep(ALTERA_PLL_WAIT_TIME_US);
 
-    bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~wrmask);
+    bus_w(cntrlReg, bus_r(cntrlReg) & ~wrmask);
-    LOG(logDEBUG2, ("Unset WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
+    LOG(logDEBUG2, ("Unset WR bit: cntrlReg:0x%x\n", bus_r(cntrlReg)));
-                    bus_r(ALTERA_PLL_Cntrl_Reg)));
 
     usleep(ALTERA_PLL_WAIT_TIME_US);
 }
 
 void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
-    LOG(logINFO, ("\tWriting PLL Phase Shift\n"));
+    LOG(logINFO, ("\tWriting PLL Phase Shift ot pll %d\n", 0));
     uint32_t value = (((phase << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST) &
                        ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK) |
                       ((clkIndex << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) &
@@ -259,19 +268,24 @@ void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
 #endif
 
     // write phase shift
-    ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value,
+    ALTERA_PLL_SetPllReconfigReg(0, ALTERA_PLL_PHASE_SHIFT_REG, value,
                                  useSecondWR);
 }
 
 void ALTERA_PLL_SetModePolling() {
     LOG(logINFO, ("\tSetting Polling Mode\n"));
-    ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG,
+    ALTERA_PLL_SetPllReconfigReg(0, ALTERA_PLL_MODE_REG,
                                  ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
 }
 
-int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
+int ALTERA_PLL_SetOuputFrequency(int pllIndex, int clkIndex, int pllVCOFreqMhz,
-    LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n",
+                                 int value) {
-                    clkIndex, value, pllVCOFreqMhz));
+    if (pllIndex == 1) {
+        clkIndex = 0;
+    }
+    LOG(logDEBUG1,
+        ("pll%d: C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n",
+         pllIndex, clkIndex, value, pllVCOFreqMhz));
 
     // calculate output frequency
     float total_div = (float)pllVCOFreqMhz / (float)value;
@@ -301,11 +315,11 @@ int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
     LOG(logDEBUG1, ("C%d word:0x%08x\n", clkIndex, val));
 
     // write frequency (post-scale output counter C)
-    ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val, 0);
+    ALTERA_PLL_SetPllReconfigReg(pllIndex, ALTERA_PLL_C_COUNTER_REG, val, 0);
 
     // reset required to keep the phase (must reconfigure adcs again after this
     // as adc clock is stopped temporarily when resetting pll)
-    ALTERA_PLL_ResetPLL();
+    ALTERA_PLL_ResetPLL(pllIndex);
 
     /*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count));
         if ((temp - (int)temp) > 0.0001) {

slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c

@@ -5689,6 +5689,9 @@ int set_clock_frequency(int file_des) {
         case DBIT_CLOCK:
             c = DBIT_CLK;
             break;
+        case GATED_CLOCK:
+            c = GATED_CLK;
+            break;
 #endif
         case RUN_CLOCK:
             c = RUN_CLK;
@@ -5750,6 +5753,9 @@ int get_clock_frequency(int file_des) {
     case DBIT_CLOCK:
         c = DBIT_CLK;
         break;
+    case GATED_CLOCK:
+        c = GATED_CLK;
+        break;
 #endif
     case RUN_CLOCK:
         c = RUN_CLK;

slsDetectorSoftware/include/sls/Detector.h

@@ -1562,6 +1562,12 @@ class Detector {
     /** [CTB][Moench] */
     void setRUNClock(int value_in_MHz, Positions pos = {});
 
+    /** [CTB] */
+    Result<int> getGatedClock(Positions pos = {}) const;
+
+    /** [CTB] */
+    void setGatedClock(int value_in_MHz, Positions pos = {});
+
     /** [CTB][Moench]  in MHZ */
     Result<int> getSYNCClock(Positions pos = {}) const;
 

slsDetectorSoftware/src/CmdProxy.h

@@ -1008,6 +1008,7 @@ class CmdProxy {
         {"asamples", &CmdProxy::asamples},
         {"adcclk", &CmdProxy::adcclk},
         {"runclk", &CmdProxy::runclk},
+        {"gatedclk", &CmdProxy::gatedclk},
         {"syncclk", &CmdProxy::syncclk},
         {"adcpipeline", &CmdProxy::adcpipeline},
         {"v_limit", &CmdProxy::v_limit},
@@ -2091,6 +2092,10 @@ class CmdProxy {
     INTEGER_COMMAND_VEC_ID(runclk, getRUNClock, setRUNClock, StringTo<int>,
                            "[n_clk in MHz]\n\t[Ctb][Moench] Run clock in MHz.");
 
+    INTEGER_COMMAND_VEC_ID(gatedclk, getGatedClock, setGatedClock,
+                           StringTo<int>,
+                           "[n_clk in MHz]\n\t[Ctb] Gated clock in MHz.");
+
     GET_COMMAND(syncclk, getSYNCClock,
                 "[n_clk in MHz]\n\t[Ctb][Moench] Sync clock in MHz.");
 

slsDetectorSoftware/src/Detector.cpp

@@ -1950,6 +1950,15 @@ void Detector::setRUNClock(int value_in_MHz, Positions pos) {
                     value_in_MHz);
 }
 
+Result<int> Detector::getGatedClock(Positions pos) const {
+    return pimpl->Parallel(&Module::getClockFrequency, pos, defs::GATED_CLOCK);
+}
+
+void Detector::setGatedClock(int value_in_MHz, Positions pos) {
+    pimpl->Parallel(&Module::setClockFrequency, pos, defs::GATED_CLOCK,
+                    value_in_MHz);
+}
+
 Result<int> Detector::getSYNCClock(Positions pos) const {
     return pimpl->Parallel(&Module::getClockFrequency, pos, defs::SYNC_CLOCK);
 }

slsSupportLib/include/sls/sls_detector_defs.h

@@ -399,7 +399,13 @@ typedef struct {
 
 #define TRIMBITMASK 0x3f
 
-    enum clockIndex { ADC_CLOCK, DBIT_CLOCK, RUN_CLOCK, SYNC_CLOCK };
+    enum clockIndex {
+        ADC_CLOCK,
+        DBIT_CLOCK,
+        RUN_CLOCK,
+        SYNC_CLOCK,
+        GATED_CLOCK
+    };
 
     /**
      * read out mode (ctb, moench)