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added gated clk for another pll for ctb
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@ -399,7 +399,13 @@ typedef struct {
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#define TRIMBITMASK 0x3f
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enum clockIndex { ADC_CLOCK, DBIT_CLOCK, RUN_CLOCK, SYNC_CLOCK };
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enum clockIndex {
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ADC_CLOCK,
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DBIT_CLOCK,
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RUN_CLOCK,
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SYNC_CLOCK,
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GATED_CLOCK
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};
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/**
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* read out mode (ctb, moench)
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