detectors/slsDetectorPackage
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added gated clk for another pll for ctb

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This commit is contained in:
maliakal_d
2022-09-28 17:35:45 +02:00
parent bac32dcba9
commit c0eeae6d6d
12 changed files with 174 additions and 85 deletions
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16
slsDetectorServers/ctbDetectorServer/RegisterDefs.h
View File

@@ -380,6 +380,22 @@
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_A_PARAM_REG (0x93 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_A_CNTRL_REG (0x94 << MEM_MAP_SHIFT)
#define PLL_A_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_A_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_A_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_A_CNTRL_WR_PRMTR_OFST (2)
#define PLL_A_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_A_CNTRL_WR_PRMTR_OFST)
#define PLL_A_CNTRL_PLL_RST_OFST (3)
#define PLL_A_CNTRL_PLL_RST_MSK (0x00000001 << PLL_A_CNTRL_PLL_RST_OFST)
#define PLL_A_CNTRL_ADDR_OFST (16)
#define PLL_A_CNTRL_ADDR_MSK (0x0000003F << PLL_A_CNTRL_ADDR_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)

64
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
View File

@@ -62,7 +62,7 @@ uint32_t adcEnableMask_1g = BIT32_MSK;
uint8_t adcEnableMask_10g = 0xFF;
int32_t clkPhase[NUM_CLOCKS] = {};
uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200};
uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200, 400};
int dacValues[NDAC] = {};
// software limit that depends on the current chip on the ctb
int vLimit = 0;
@@ -471,6 +471,7 @@ void setupDetector() {
clkFrequency[ADC_CLK] = DEFAULT_ADC_CLK;
clkFrequency[SYNC_CLK] = DEFAULT_SYNC_CLK;
clkFrequency[DBIT_CLK] = DEFAULT_DBIT_CLK;
clkFrequency[GATED_CLK] = DEFAULT_GATED_CLK;
for (int i = 0; i < NDAC; ++i)
dacValues[i] = -1;
}
@@ -488,7 +489,15 @@ void setupDetector() {
#endif
setupUDPCommParameters();
ALTERA_PLL_ResetPLLAndReconfiguration();
// altera pll
ALTERA_PLL_SetDefines(
PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK,
PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST, PLL_A_CNTRL_REG, PLL_A_PARAM_REG);
// both plls
ALTERA_PLL_ResetPLLAndReconfiguration(0);
ALTERA_PLL_ResetPLLAndReconfiguration(1);
resetCore();
resetPeripheral();
cleanFifos();
@@ -548,12 +557,6 @@ void setupDetector() {
INA226_CalibrateCurrentRegister(I2C_POWER_VD_DEVICE_ID);
setVchip(VCHIP_MIN_MV);
// altera pll
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG,
PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK,
PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST);
setADCInvertRegister(0); // depends on chip
LOG(logINFOBLUE, ("Setting Default parameters\n"));
@@ -1784,34 +1787,45 @@ int setFrequency(enum CLKINDEX ind, int val) {
return FAIL;
}
int pllIndex = 0;
int vcofreq = PLL_VCO_FREQ_MHZ;
if (ind == GATED_CLK) {
pllIndex = 1;
vcofreq = PLL_A_VCO_FREQ_MHZ;
}
// Remembering adcphase/ dbit phase in degrees
int adcPhase = getPhase(ADC_CLK, 1);
LOG(logDEBUG1, ("\tRemembering ADC phase: %d degrees\n", adcPhase));
int dbitPhase = getPhase(DBIT_CLK, 1);
LOG(logDEBUG1, ("\tRemembering DBIT phase: %d degrees\n", dbitPhase));
int adcPhase = 0, dbitPhase = 0;
if (pllIndex == 0) {
adcPhase = getPhase(ADC_CLK, 1);
LOG(logDEBUG1, ("\tRemembering ADC phase: %d degrees\n", adcPhase));
dbitPhase = getPhase(DBIT_CLK, 1);
LOG(logDEBUG1, ("\tRemembering DBIT phase: %d degrees\n", dbitPhase));
}
// Calculate and set output frequency
clkFrequency[ind] =
ALTERA_PLL_SetOuputFrequency(ind, PLL_VCO_FREQ_MHZ, val);
ALTERA_PLL_SetOuputFrequency(pllIndex, ind, vcofreq, val);
LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind],
ind, clkFrequency[ind]));
// phase reset by pll (when setting output frequency)
clkPhase[ADC_CLK] = 0;
clkPhase[DBIT_CLK] = 0;
if (pllIndex == 0) {
clkPhase[ADC_CLK] = 0;
clkPhase[DBIT_CLK] = 0;
// set the phase (reset by pll)
LOG(logINFO, ("\tCorrecting ADC phase to %d degrees\n", adcPhase));
setPhase(ADC_CLK, adcPhase, 1);
LOG(logINFO, ("\tCorrecting DBIT phase to %d degrees\n", dbitPhase));
setPhase(DBIT_CLK, dbitPhase, 1);
// set the phase (reset by pll)
LOG(logINFO, ("\tCorrecting ADC phase to %d degrees\n", adcPhase));
setPhase(ADC_CLK, adcPhase, 1);
LOG(logINFO, ("\tCorrecting DBIT phase to %d degrees\n", dbitPhase));
setPhase(DBIT_CLK, dbitPhase, 1);
// required to reconfigure as adc clock is stopped temporarily when
// resetting pll (in changing output frequency)
AD9257_Configure();
// required to reconfigure as adc clock is stopped temporarily when
// resetting pll (in changing output frequency)
AD9257_Configure();
if (ind != SYNC_CLK) {
configureSyncFrequency(ind);
if (ind != SYNC_CLK) {
configureSyncFrequency(ind);
}
}
return OK;
}

10
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
View File

@@ -86,8 +86,8 @@ enum DACINDEX {
D_PWR_A,
D_PWR_IO
};
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, GATED_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit", "gated"
/* Hardware Definitions */
#define NCHAN (36)
@@ -124,6 +124,7 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define DEFAULT_ADC_CLK (40) // 20
#define DEFAULT_SYNC_CLK (40) // 20
#define DEFAULT_DBIT_CLK (200)
#define DEFAULT_GATED_CLK (400)
#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
@@ -160,5 +161,6 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)
#define PLL_A_VCO_FREQ_MHZ (400)