From bf4ba9d08bcdf5e3bd68d8dac85398245d88ff51 Mon Sep 17 00:00:00 2001 From: Dhanya Thattil Date: Tue, 8 Jan 2019 06:57:04 +0100 Subject: [PATCH] some minor modifications --- .../gotthardDetectorServer/RegisterDefs.h | 2 +- .../gotthardDetectorServer/slsDetectorFunctionList.c | 12 ++---------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/slsDetectorServers/gotthardDetectorServer/RegisterDefs.h b/slsDetectorServers/gotthardDetectorServer/RegisterDefs.h index aff91a63f..394350b17 100755 --- a/slsDetectorServers/gotthardDetectorServer/RegisterDefs.h +++ b/slsDetectorServers/gotthardDetectorServer/RegisterDefs.h @@ -111,7 +111,7 @@ //0x32214 #define ADC_SYNC_TKN_VAL (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | ADC_SYNC_TKN2_LOW_DLY_VAL) #define ADC_SYNC_CLEAN_FIFOS_OFST (20) -#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)// FIXME: tried with 1, works? else put 0x011 as mask +#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST) #define ADC_SYNC_ENET_DELAY_OFST (24) #define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST) #define ADC_SYNC_ENET_DELAY_NO_ROI_VAL ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK) diff --git a/slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c index 173f5e95f..7e6aa3661 100644 --- a/slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c @@ -401,7 +401,7 @@ void setupDetector() { setROIADC(-1); // set adcsyncreg, daqreg, chipofinterestreg, cleanfifos, setGbitReadout(); - LTC2620_Configure(); /*FIXME: if it doesnt work, switch to the old dac*/ + LTC2620_Configure(); // master, slave (25um) setMasterSlaveConfiguration(); @@ -1403,10 +1403,6 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t bus_w(addr, bus_r(addr) &(~WRT_BCK_MSK)); FILE_LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr))); - // nreset phy /*FIXME: is this needed ?? */ - /* bus_w(addr, bus_r(addr) | ENT_RSTN_MSK); - FILE_LOG(logDEBUG1, ("\tNreset phy. MultiPurpose reg: 0x%x\n", bus_r(addr)));*/ - FILE_LOG(logDEBUG1, ("\tConfiguring MAC CONF\n")); mac_conf *mac_conf_regs = (mac_conf*)(CSP0BASE + ENET_CONF_REG * 2); // direct write mac_conf_regs->mac.mac_dest_mac1 = ((destmac >> (8 * 5)) & 0xFF); @@ -1466,8 +1462,6 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t tse_conf_regs->mdio_addr1 = 0x0; mac_conf_regs->cdone = 0xFFFFFFFF; - // write shadow regs /* FIXME: Only INT_RSTN_MSK | WRT_BCK_MSK */ - /*bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK| WRT_BCK_MSK));*/ bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | WRT_BCK_MSK)); FILE_LOG(logDEBUG1, ("\tWrite shadow regs with int reset. MultiPurpose reg: 0x%x\n", bus_r(addr))); @@ -1477,8 +1471,6 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t bus_w(addr, bus_r(addr) &(~WRT_BCK_MSK)); FILE_LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr))); - // sw1 /* FIXME: Only SW1_MSK */ - /*bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK | SW1_MSK));*/ bus_w(addr, bus_r(addr) | SW1_MSK); FILE_LOG(logDEBUG1, ("\tSw1. MultiPurpose reg: 0x%x\n", bus_r(addr))); @@ -1643,7 +1635,7 @@ int stopStateMachine(){ #endif //stop state machine bus_w16(CONTROL_REG, CONTROL_STP_ACQ_MSK); - //usleep(100);/**FIXME:Needed? not there earlier*/ + usleep(100); bus_w16(CONTROL_REG, 0x0); // check