mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-21 17:18:00 +02:00
set clock divider, phase and get clock freq for gotthard2, priliminary
This commit is contained in:
195
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c
Executable file
195
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c
Executable file
@ -0,0 +1,195 @@
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#include "ALTERA_PLL_CYCLONE10.h"
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#include "clogger.h"
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#include "nios.h"
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#include "sls_detector_defs.h"
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#include <unistd.h> // usleep
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/* Altera PLL CYCLONE 10 DEFINES */
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/** PLL Reconfiguration Registers */
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// https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an728.pdf
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// c counter (C0-C8 (+1 to base address))
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#define ALTERA_PLL_C10_C_COUNTER_BASE_REG (0x0C0)
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#define ALTERA_PLL_C10_C_COUNTER_MAX_DIVIDER_VAL (0xFF)
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#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST (0)
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#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST)
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#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST (8)
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#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST)
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/* total_div = lw_cnt + hgh_cnt */
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#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST (16)
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#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_MSK (0x00000001 << ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST)
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/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
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#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST (17)
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#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK (0x00000001 << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST)
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/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
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// dynamic phase shift (C0-C8 (+1 to base address), 0xF for all counters)
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#define ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG (0x100)
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#define ALTERA_PLL_C10_MAX_SHIFTS_PER_OPERATION (7)
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#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST (0)
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#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK (0x00000007 << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST)
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#define ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST (3)
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#define ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK (0x00000001 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST)
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#define ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL ((0x0 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
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#define ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL ((0x1 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
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#define ALTERA_PLL_C10_PHASE_SHIFT_STEP_OF_VCO (8)
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#define ALTERA_PLL_C10_WAIT_TIME_US (10 * 1000)
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int ALTERA_PLL_C10_Reg_offset = 0x0;
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const int ALTERA_PLL_C10_NUM = 2;
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uint32_t ALTERA_PLL_C10_BaseAddress[2] = {0x0, 0x0};
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uint32_t ALTERA_PLL_C10_Reset_Reg[2] = {0x0, 0x0};
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uint32_t ALTERA_PLL_C10_Reset_Msk[2] = {0x0, 0x0};
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uint32_t ALTERA_PLL_C10_Wait_Reg[2] = {0x0, 0x0};
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uint32_t ALTERA_PLL_C10_Wait_Msk[2] = {0x0, 0x0};
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int ALTERA_PLL_C10_VCO_FREQ[2] = {0, 0};
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void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0, uint32_t baseaddr1, uint32_t resetreg0, uint32_t resetreg1, uint32_t resetmsk0, uint32_t resetmsk1, uint32_t waitreg0, uint32_t waitreg1, uint32_t waitmsk0, uint32_t waitmsk1, int vcofreq0, int vcofreq1) {
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ALTERA_PLL_C10_Reg_offset = regofst;
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ALTERA_PLL_C10_BaseAddress[0] = baseaddr0;
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ALTERA_PLL_C10_BaseAddress[1] = baseaddr1;
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ALTERA_PLL_C10_Reset_Reg[0] = resetreg0;
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ALTERA_PLL_C10_Reset_Reg[1] = resetreg1;
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ALTERA_PLL_C10_Reset_Msk[0] = resetmsk0;
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ALTERA_PLL_C10_Reset_Msk[1] = resetmsk1;
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ALTERA_PLL_C10_Wait_Reg[0] = waitreg0;
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ALTERA_PLL_C10_Wait_Reg[1] = waitreg1;
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ALTERA_PLL_C10_Wait_Msk[0] = waitmsk0;
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ALTERA_PLL_C10_Wait_Msk[1] = waitmsk1;
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ALTERA_PLL_C10_VCO_FREQ[0] = vcofreq0;
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ALTERA_PLL_C10_VCO_FREQ[1] = vcofreq1;
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}
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int ALTERA_PLL_C10_GetMaxClockDivider() {
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return ALTERA_PLL_C10_C_COUNTER_MAX_DIVIDER_VAL;
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}
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int ALTERA_PLL_C10_GetVCOFrequency(int pllIndex) {
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return ALTERA_PLL_C10_VCO_FREQ[pllIndex];
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}
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int ALTERA_PLL_C10_GetMaxPhaseShiftStepsofVCO() {
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return ALTERA_PLL_C10_PHASE_SHIFT_STEP_OF_VCO;
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}
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int ALTERA_PLL_C10_Reconfigure(int pllIndex) {
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FILE_LOG(logINFO, ("\tReconfiguring PLL %d\n", pllIndex));
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uint32_t waitreg = ALTERA_PLL_C10_Wait_Reg[pllIndex];
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uint32_t waitmsk = ALTERA_PLL_C10_Wait_Msk[pllIndex];
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// write anything to base address to start reconfiguring
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FILE_LOG(logDEBUG1, ("\tWriting 1 to base address 0x%x to start reconfiguring\n", ALTERA_PLL_C10_BaseAddress[pllIndex]));
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//bus_w_csp1(ALTERA_PLL_C10_BaseAddress[pllIndex], 0x1);
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// wait for write operation to be completed by polling wait request bit
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int ret = OK;
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FILE_LOG(logDEBUG1, ("\tWaiting a second (instead of wait request bit in fw)\n"));
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usleep(1 * 1000 * 1000);
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/* TODO wait reg and wait mask to be done in firware, so wait instead (above)
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int counter = 0;
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while (bus_r_csp1(waitreg) & waitmsk) {
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usleep(ALTERA_PLL_C10_WAIT_TIME_US);
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++counter;
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if (counter >= 100) {
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FILE_LOG(logERROR, ("Waited for the pll wait request for 1 s. Not waiting anymore."));
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ret = FAIL;
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break;
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}
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}
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FILE_LOG(logINFO, ("\tReconfiguring PLL %d done with %s\n", pllIndex, ret == FAIL ? "failure" : "success"));
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*/
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FILE_LOG(logDEBUG1, ("\tWaiting done\n"));
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return ret;
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}
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void ALTERA_PLL_C10_ResetPLL (int pllIndex) {
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FILE_LOG(logINFO, ("Resetting PLL %d\n", pllIndex));
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uint32_t resetreg = ALTERA_PLL_C10_Reset_Reg[pllIndex];
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uint32_t resetmsk = ALTERA_PLL_C10_Reset_Msk[pllIndex];
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FILE_LOG(logERROR, ("Reset not implemented yet!\n"));
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/* TODO reset reg and reset mask to be done in firware, so wait instead (above)
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bus_w_csp1(resetreg, bus_r_csp1(resetreg) | resetmsk);
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usleep(ALTERA_PLL_C10_WAIT_TIME_US); //FIXME
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bus_w_csp1(resetreg, bus_r_csp1(resetreg) & ~resetmsk);//FIXME
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*/
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}
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int ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos) {
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FILE_LOG(logINFO, ("\tC%d: Writing PLL %d Phase Shift [phase:%d, pos:%d]\n", clkIndex, pllIndex, phase, pos));
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FILE_LOG(logDEBUG1, ("\tBase address: 0x%x phasebasereg:0x%x\n", ALTERA_PLL_C10_BaseAddress[pllIndex], ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG));
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uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] + (ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG + (int)clkIndex) * ALTERA_PLL_C10_Reg_offset;
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int maxshifts = ALTERA_PLL_C10_MAX_SHIFTS_PER_OPERATION;
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// only 7 shifts at a time
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int ret = OK;
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while (phase > 0) {
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int phaseToDo = (phase > maxshifts) ? maxshifts : phase;
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uint32_t value = (((phaseToDo << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST) & ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK) |
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(pos ? ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL : ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL));
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FILE_LOG(logDEBUG1, ("\t[addr:0x%x, phaseTodo:%d phaseleft:%d phase word:0x%08x]\n", addr, phaseToDo, phase, value));
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//bus_w_csp1(addr, value);
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if (ALTERA_PLL_C10_Reconfigure(pllIndex) == FAIL) {
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ret = FAIL;
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}
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phase -= phaseToDo;
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}
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return ret;
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}
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int ALTERA_PLL_C10_SetOuputFrequency (int pllIndex, int clkIndex, int value) {
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int pllVCOFreqHz = ALTERA_PLL_C10_VCO_FREQ[pllIndex];
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FILE_LOG(logDEBUG1, ("\tC%d: Setting output frequency for pll %d to %d (pllvcofreq: %dHz)\n", clkIndex, pllIndex, value, pllVCOFreqHz));
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// calculate output frequency
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float total_div = (float)pllVCOFreqHz / (float)value;
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// assume 50% duty cycle
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uint32_t low_count = total_div / 2;
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uint32_t high_count = low_count;
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uint32_t odd_division = 0;
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// odd division
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if (total_div > (float)(2 * low_count)) {
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++high_count;
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odd_division = 1;
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}
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FILE_LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count, high_count, odd_division));
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// command to set output frequency
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uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] + (ALTERA_PLL_C10_C_COUNTER_BASE_REG + (int)clkIndex) * ALTERA_PLL_C10_Reg_offset;
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uint32_t val = (((low_count << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST) & ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK) |
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((high_count << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST) & ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK) |
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((odd_division << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST) & ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK));
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FILE_LOG(logDEBUG1, ("\t[addr:0x%x, word:0x%08x]\n", addr, val));
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// write frequency
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//bus_w_csp1(addr, val);
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int ret = ALTERA_PLL_C10_Reconfigure(pllIndex);
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// reset required to keep the phase relationships (must reconfigure adcs again after this as adc clock is stopped temporarily when resetting pll)
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ALTERA_PLL_C10_ResetPLL (pllIndex);
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return ret;
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}
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@ -12,6 +12,20 @@ u_int32_t* csp0base = 0;
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#define CSP0 0x18060000
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#define MEM_SIZE 0x100000
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u_int32_t* csp1base = 0;
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#define CSP1 0x18040000
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void bus_w_csp1(u_int32_t offset, u_int32_t data) {
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volatile u_int32_t *ptr1;
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ptr1=(u_int32_t*)(csp1base + offset/(sizeof(u_int32_t)));
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*ptr1=data;
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}
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u_int32_t bus_r_csp1(u_int32_t offset) {
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volatile u_int32_t *ptr1;
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ptr1=(u_int32_t*)(csp1base + offset/(sizeof(u_int32_t)));
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return *ptr1;
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}
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void bus_w(u_int32_t offset, u_int32_t data) {
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volatile u_int32_t *ptr1;
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@ -72,38 +86,46 @@ u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
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int mapCSP0(void) {
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// if not mapped
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if (csp0base == 0) {
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FILE_LOG(logINFO, ("Mapping memory\n"));
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u_int32_t csps[2] = {CSP0, CSP1};
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u_int32_t** cspbases[2] = {&csp0base, &csp1base};
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char names[2][10]={"csp0base","csp1base"};
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int i = 0;
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for (i = 0; i < 2; ++i) {
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// if not mapped
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if (*cspbases[i] == 0) {
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FILE_LOG(logINFO, ("Mapping memory for %s\n", names[i]));
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#ifdef VIRTUAL
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csp0base = malloc(MEM_SIZE);
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if (csp0base == NULL) {
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FILE_LOG(logERROR, ("Could not allocate virtual memory.\n"));
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return FAIL;
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}
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FILE_LOG(logINFO, ("memory allocated\n"));
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*cspbases[i] = malloc(MEM_SIZE);
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if (*cspbases[i] == NULL) {
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FILE_LOG(logERROR, ("Could not allocate virtual memory for %s.\n", names[i]));
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return FAIL;
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}
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FILE_LOG(logINFO, ("memory allocated for %s\n", names[i]));
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#else
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int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
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if (fd == -1) {
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FILE_LOG(logERROR, ("Can't find /dev/mem\n"));
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return FAIL;
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}
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FILE_LOG(logDEBUG1, ("/dev/mem opened\n"));
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csp0base = (u_int32_t*)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, CSP0);
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if (csp0base == MAP_FAILED) {
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FILE_LOG(logERROR, ("Can't map memmory area\n"));
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return FAIL;
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}
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int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
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if (fd == -1) {
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FILE_LOG(logERROR, ("Can't find /dev/mem for %s\n", names[i]));
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return FAIL;
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}
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FILE_LOG(logDEBUG1, ("/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
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*cspbases[i] = (u_int32_t*)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, csps[i]);
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if (*cspbases[i] == MAP_FAILED) {
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FILE_LOG(logERROR, ("Can't map memmory area for %s\n", names[i]));
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return FAIL;
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}
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#endif
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FILE_LOG(logINFO, ("CSPOBASE mapped from 0x%p to 0x%p\n",
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csp0base, csp0base+MEM_SIZE));
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//FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
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}else
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FILE_LOG(logINFO, ("Memory already mapped before\n"));
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FILE_LOG(logINFO, ("%s mapped from %p to %p,(CSP:0x%x) \n",
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names[i], *cspbases[i], *cspbases[i]+MEM_SIZE, csps[i]));
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//FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
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} else
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FILE_LOG(logINFO, ("Memory %s already mapped before\n", names[i]));
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}
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return OK;
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}
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u_int32_t* Nios_getBaseAddress() {
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return csp0base;
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}
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@ -284,6 +284,15 @@ const char* getFunctionName(enum detFuncs func) {
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case F_GET_STOREINRAM_MODE: return "F_GET_STOREINRAM_MODE";
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case F_SET_READOUT_MODE: return "F_SET_READOUT_MODE";
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case F_GET_READOUT_MODE: return "F_GET_READOUT_MODE";
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case F_SET_CLOCK_FREQUENCY: return "F_SET_CLOCK_FREQUENCY";
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case F_GET_CLOCK_FREQUENCY: return "F_GET_CLOCK_FREQUENCY";
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case F_SET_CLOCK_PHASE: return "F_SET_CLOCK_PHASE";
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case F_GET_CLOCK_PHASE: return "F_GET_CLOCK_PHASE";
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case F_GET_MAX_CLOCK_PHASE_SHIFT: return "F_GET_MAX_CLOCK_PHASE_SHIFT";
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case F_SET_CLOCK_DIVIDER: return "F_SET_CLOCK_DIVIDER";
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case F_GET_CLOCK_DIVIDER: return "F_GET_CLOCK_DIVIDER";
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default: return "Unknown Function";
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}
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}
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@ -403,6 +412,13 @@ void function_table() {
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flist[F_GET_STOREINRAM_MODE] = &get_storeinram;
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flist[F_SET_READOUT_MODE] = &set_readout_mode;
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flist[F_GET_READOUT_MODE] = &get_readout_mode;
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flist[F_SET_CLOCK_FREQUENCY] = &set_clock_frequency;
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flist[F_GET_CLOCK_FREQUENCY] = &get_clock_frequency;
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flist[F_SET_CLOCK_PHASE] = &set_clock_phase;
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flist[F_GET_CLOCK_PHASE] = &get_clock_phase;
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flist[F_GET_MAX_CLOCK_PHASE_SHIFT] = &get_max_clock_phase_shift;
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flist[F_SET_CLOCK_DIVIDER] = &set_clock_divider;
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flist[F_GET_CLOCK_DIVIDER] = &get_clock_divider;
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// check
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if (NUM_DET_FUNCTIONS >= RECEIVER_ENUM_START) {
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@ -4830,11 +4846,11 @@ int get_dest_udp_port(int file_des) {
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ret = OK;
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memset(mess, 0, sizeof(mess));
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int retval = -1;
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FILE_LOG(logDEBUG1, ("Getting destination port\n"));
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FILE_LOG(logDEBUG1, ("Getting destination porstore in ram moden"));
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// get only
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retval = udpDetails.dstport;
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FILE_LOG(logDEBUG, ("udp destination port retval: %u\n", retval));
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FILE_LOG(logDEBUG, ("udp destination port retstore in ram model: %u\n", retval));
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||||
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
|
||||
}
|
||||
@ -5184,3 +5200,267 @@ int get_readout_mode(int file_des) {
|
||||
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int set_clock_frequency(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int args[2] = {-1, -1};
|
||||
|
||||
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logINFO, ("Setting frequency of clock %d: %u\n", args[0], args[1]));
|
||||
|
||||
|
||||
functionNotImplemented();
|
||||
/*
|
||||
// only set
|
||||
if (Server_VerifyLock() == OK) {
|
||||
enum CLKINDEX c = (enum CLKINDEX)args[0];
|
||||
if (c >= NUM_CLOCKS) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot set frequency of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
ret = setFrequency(c, args[1]);
|
||||
if (ret == FAIL) {
|
||||
strcpy(mess, "Set frequency in unknown state. Reconfigure did not return.\n");
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
int retval = getFrequency(c);
|
||||
FILE_LOG(logDEBUG1, ("retval frequency of clock %d: %d\n", (int)c, retval));
|
||||
|
||||
char cval[100];
|
||||
memset(cval, 0, 100);
|
||||
sprintf(cval, "set frequency of clock %d Hz", (int)c);
|
||||
validate(args[1], retval, cval, DEC);
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
|
||||
}
|
||||
|
||||
|
||||
int get_clock_frequency(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int arg = -1;
|
||||
int retval = -1;
|
||||
|
||||
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Getting frequency of clock %d\n", arg));
|
||||
|
||||
#ifndef GOTTHARD2D
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
enum CLKINDEX c = (enum CLKINDEX)arg;
|
||||
if (c >= NUM_CLOCKS) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot get frequency of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
retval = getFrequency(c);
|
||||
FILE_LOG(logDEBUG1, ("retval frequency of clock %d Hz: %d\n", (int)c, retval));
|
||||
}
|
||||
#endif
|
||||
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
int set_clock_phase(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int args[3] = {-1, -1, -1};
|
||||
|
||||
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logINFO, ("Setting phase of clock %d: %u %s\n", args[0], args[1], (args[2] == 0 ? "" : "degrees")));
|
||||
|
||||
#ifndef GOTTHARD2D
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// only set
|
||||
if (Server_VerifyLock() == OK) {
|
||||
enum CLKINDEX c = (enum CLKINDEX)args[0];
|
||||
if (c >= NUM_CLOCKS) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot set phase for clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
int val = args[1];
|
||||
int degrees = args[2];
|
||||
if (degrees && (val < 0 || val > 359)) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot set phase. Phase provided for C%d outside limits (0 - 359°C)\n", (int)c);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else if (!degrees && (val < 0 || val > getMaxPhase(c) - 1)) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot set phase. Phase provided for C%d outside limits (0 - %d phase shifts)\n", (int)c, getMaxPhase(c) - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
ret = setPhase(c, val, degrees);
|
||||
if (ret == FAIL) {
|
||||
strcpy(mess, "Set phase in unknown state. Reconfigure did not return.\n");
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
int retval = getPhase(c, degrees);
|
||||
FILE_LOG(logDEBUG1, ("retval phase for clock %d: %d %s \n", (int)c, retval, (degrees == 0 ? "" : "degrees")));
|
||||
|
||||
char cval[100];
|
||||
memset(cval, 0, 100);
|
||||
sprintf(cval, "set phase for clock %d",(int)c);
|
||||
if (!degrees) {
|
||||
validate(val, retval, cval, DEC);
|
||||
} else {
|
||||
ret = validatePhaseinDegrees(c, val, retval);
|
||||
if (ret == FAIL) {
|
||||
sprintf(mess, "Could not set %s. Set %d degrees, got %d degrees\n", cval, val, retval);
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
|
||||
}
|
||||
|
||||
|
||||
int get_clock_phase(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int args[2] = {-1, -1};
|
||||
int retval = -1;
|
||||
|
||||
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Getting phase for clock %d %s \n", args[0], (args[1] == 0 ? "" : "in degrees")));
|
||||
|
||||
#ifndef GOTTHARD2D
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
enum CLKINDEX c = (enum CLKINDEX)args[0];
|
||||
if (c >= NUM_CLOCKS) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot get phase of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
retval = getPhase(c, args[1]);
|
||||
FILE_LOG(logDEBUG1, ("retval phase for clock %d: %d %s\n", (int)c, retval, (args[1] == 0 ? "" : "degrees")));
|
||||
}
|
||||
#endif
|
||||
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
|
||||
}
|
||||
|
||||
|
||||
int get_max_clock_phase_shift(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int arg = -1;
|
||||
int retval = -1;
|
||||
|
||||
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Getting max phase shift of clock %d\n", arg));
|
||||
|
||||
#ifndef GOTTHARD2D
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
enum CLKINDEX c = (enum CLKINDEX)arg;
|
||||
if (c >= NUM_CLOCKS) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot get frequency of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
retval = getMaxPhase(c);
|
||||
FILE_LOG(logDEBUG1, ("retval max phase shift of clock %d: %d\n", (int)c, retval));
|
||||
}
|
||||
#endif
|
||||
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
|
||||
}
|
||||
|
||||
|
||||
int set_clock_divider(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int args[2] = {-1, -1};
|
||||
|
||||
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logINFO, ("Setting divider of clock %d: %u\n", args[0], args[1]));
|
||||
|
||||
#ifndef GOTTHARD2D
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// only set
|
||||
if (Server_VerifyLock() == OK) {
|
||||
enum CLKINDEX c = (enum CLKINDEX)args[0];
|
||||
int val = args[1];
|
||||
if (c >= NUM_CLOCKS) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot set divider of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else if (getClockDivider(c) == val) {
|
||||
FILE_LOG(logINFO, ("Same clock divider %d\n"));
|
||||
} else if (val < 2 || val > getMaxClockDivider()) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot set divider of clock %d to %d. Value should be in range [2-%d]\n", (int)c, val, getMaxClockDivider());
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
ret = setClockDivider(c, val);
|
||||
if (ret == FAIL) {
|
||||
strcpy(mess, "Set divider in unknown state. Reconfigure did not return.\n");
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
int retval = getClockDivider(c);
|
||||
FILE_LOG(logDEBUG1, ("retval divider of clock %d: %d\n", (int)c, retval));
|
||||
|
||||
char cval[100];
|
||||
memset(cval, 0, 100);
|
||||
sprintf(cval, "set divider of clock %d Hz", (int)c);
|
||||
validate(val, retval, cval, DEC);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
|
||||
}
|
||||
|
||||
|
||||
int get_clock_divider(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int arg = -1;
|
||||
int retval = -1;
|
||||
|
||||
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Getting divider of clock %d\n", arg));
|
||||
|
||||
#ifndef GOTTHARD2D
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
enum CLKINDEX c = (enum CLKINDEX)arg;
|
||||
if (c >= NUM_CLOCKS) {
|
||||
ret = FAIL;
|
||||
sprintf(mess, "Cannot get divider of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
|
||||
FILE_LOG(logERROR, (mess));
|
||||
} else {
|
||||
retval = getClockDivider(c);
|
||||
FILE_LOG(logDEBUG1, ("retval divider of clock %d Hz: %d\n", (int)c, retval));
|
||||
}
|
||||
#endif
|
||||
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user