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move pattern loopdef start
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muelle_m1 2025-05-16 15:58:42 +02:00
parent b8204b757e
commit bcf63b7eda
1 changed files with 31 additions and 31 deletions
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62
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
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@ -294,7 +294,7 @@
#define FRAME_TIME_OUT_REG_2 (0xB090) #define FRAME_TIME_OUT_REG_2 (0xB090)
#define PATTERN_LOOPDEF_START_REG (0xB100) #define PATTERN_LOOPDEF_START_REG (0xB080)
#define PATTERN_LOOPDEF_LOOP_ADDR_OFST (0) #define PATTERN_LOOPDEF_LOOP_ADDR_OFST (0)
#define PATTERN_LOOPDEF_LOOP_ADDR_MSK (0x00000001 << PATTERN_LOOPDEF_LOOP_ADDR_OFST) #define PATTERN_LOOPDEF_LOOP_ADDR_MSK (0x00000001 << PATTERN_LOOPDEF_LOOP_ADDR_OFST)
@ -464,24 +464,24 @@
//----------------------------------- //-----------------------------------
#define PINIOCTRLREG (0xB028) #define PINIOCTRLREG (0xB028)
#define PATTERN_LOOP_0_ADDR_REG (0xB100) #define PATTERN_LOOP_0_ADDR_REG (0xB080)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0) #define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \ #define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST) (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16) #define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST) #define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
#define PATTERN_LOOP_0_ITERATION_REG (0xB104) #define PATTERN_LOOP_0_ITERATION_REG (0xB084)
#define PATTERN_WAIT_0_ADDR_REG (0xB108) #define PATTERN_WAIT_0_ADDR_REG (0xB088)
#define PATTERN_WAIT_0_ADDR_OFST (0) #define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST) #define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST)
#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB10C) #define PATTERN_WAIT_TIMER_0_LSB_REG (0xB08C)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB110) #define PATTERN_WAIT_TIMER_0_MSB_REG (0xB090)
#define PATTERN_LOOP_1_ADDR_REG (0xB114) #define PATTERN_LOOP_1_ADDR_REG (0xB094)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0) #define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \ #define PATTERN_LOOP_1_ADDR_STRT_MSK \
@ -489,18 +489,18 @@
#define PATTERN_LOOP_1_ADDR_STP_OFST (16) #define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST) #define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
#define PATTERN_LOOP_1_ITERATION_REG (0xB118) #define PATTERN_LOOP_1_ITERATION_REG (0xB098)
#define PATTERN_WAIT_1_ADDR_REG (0xB11C) #define PATTERN_WAIT_1_ADDR_REG (0xB09C)
#define PATTERN_WAIT_1_ADDR_OFST (0) #define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST) #define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST)
#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB120) #define PATTERN_WAIT_TIMER_1_LSB_REG (0xB0A0)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB124) #define PATTERN_WAIT_TIMER_1_MSB_REG (0xB0A4)
#define PATTERN_LOOP_2_ADDR_REG (0xB128) #define PATTERN_LOOP_2_ADDR_REG (0xB0A8)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0) #define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \ #define PATTERN_LOOP_2_ADDR_STRT_MSK \
@ -508,18 +508,18 @@
#define PATTERN_LOOP_2_ADDR_STP_OFST (16) #define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST) #define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
#define PATTERN_LOOP_2_ITERATION_REG (0xB12C) #define PATTERN_LOOP_2_ITERATION_REG (0xB0AC)
#define PATTERN_WAIT_2_ADDR_REG (0xB130) #define PATTERN_WAIT_2_ADDR_REG (0xB0B0)
#define PATTERN_WAIT_2_ADDR_OFST (0) #define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST) #define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST)
#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB134) #define PATTERN_WAIT_TIMER_2_LSB_REG (0xB0B4)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB138) #define PATTERN_WAIT_TIMER_2_MSB_REG (0xB0B8)
#define PATTERN_LOOP_3_ADDR_REG (0xB13C) #define PATTERN_LOOP_3_ADDR_REG (0xB0BC)
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0) #define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_3_ADDR_STRT_MSK \ #define PATTERN_LOOP_3_ADDR_STRT_MSK \
@ -527,18 +527,18 @@
#define PATTERN_LOOP_3_ADDR_STP_OFST (16) #define PATTERN_LOOP_3_ADDR_STP_OFST (16)
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST) #define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
#define PATTERN_LOOP_3_ITERATION_REG (0xB140) #define PATTERN_LOOP_3_ITERATION_REG (0xB0C0)
#define PATTERN_WAIT_3_ADDR_REG (0xB144) #define PATTERN_WAIT_3_ADDR_REG (0xB0C4)
#define PATTERN_WAIT_3_ADDR_OFST (0) #define PATTERN_WAIT_3_ADDR_OFST (0)
#define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST) #define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST)
#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB148) #define PATTERN_WAIT_TIMER_3_LSB_REG (0xB0C8)
#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB14C) #define PATTERN_WAIT_TIMER_3_MSB_REG (0xB0CC)
#define PATTERN_LOOP_4_ADDR_REG (0xB150) #define PATTERN_LOOP_4_ADDR_REG (0xB0D0)
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0) #define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_4_ADDR_STRT_MSK \ #define PATTERN_LOOP_4_ADDR_STRT_MSK \
@ -546,18 +546,18 @@
#define PATTERN_LOOP_4_ADDR_STP_OFST (16) #define PATTERN_LOOP_4_ADDR_STP_OFST (16)
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST) #define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
#define PATTERN_LOOP_4_ITERATION_REG (0xB154) #define PATTERN_LOOP_4_ITERATION_REG (0xB0D4)
#define PATTERN_WAIT_4_ADDR_REG (0xB158) #define PATTERN_WAIT_4_ADDR_REG (0xB0D8)
#define PATTERN_WAIT_4_ADDR_OFST (0) #define PATTERN_WAIT_4_ADDR_OFST (0)
#define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST) #define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST)
#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB15C) #define PATTERN_WAIT_TIMER_4_LSB_REG (0xB0DC)
#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB160) #define PATTERN_WAIT_TIMER_4_MSB_REG (0xB0E0)
#define PATTERN_LOOP_5_ADDR_REG (0xB164) #define PATTERN_LOOP_5_ADDR_REG (0xB0E4)
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0) #define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_5_ADDR_STRT_MSK \ #define PATTERN_LOOP_5_ADDR_STRT_MSK \
@ -565,10 +565,10 @@
#define PATTERN_LOOP_5_ADDR_STP_OFST (16) #define PATTERN_LOOP_5_ADDR_STP_OFST (16)
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST) #define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
#define PATTERN_LOOP_5_ITERATION_REG (0xB168) #define PATTERN_LOOP_5_ITERATION_REG (0xB0E8)
#define PATTERN_WAIT_5_ADDR_REG (0xB16C) #define PATTERN_WAIT_5_ADDR_REG (0xB0EC)
#define PATTERN_WAIT_5_ADDR_OFST (0) #define PATTERN_WAIT_5_ADDR_OFST (0)
#define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST) #define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST)
#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB170) #define PATTERN_WAIT_TIMER_5_LSB_REG (0xB0F0)
#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB174) #define PATTERN_WAIT_TIMER_5_MSB_REG (0xB0F4)