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ctb server: altera pll odd division fix

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maliakal_d
2019-03-21 14:13:07 +01:00
parent 050854de36
commit b99606211b
3 changed files with 10 additions and 10 deletions
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8
slsDetectorServers/ctbDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 44f0dfc3c00d0dd70a683289dde9a2fcbf1e0449 Repsitory UUID: 050854de36f01379e974005e204b6563ffbc7004
Revision: 42 Revision: 43
Branch: refactor Branch: refactor
Last Changed Author: Dhanya_Thattil Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4450 Last Changed Rev: 4458
Last Changed Date: 2019-03-20 12:35:24.000000002 +0100 ./slsDetectorFunctionList.c Last Changed Date: 2019-03-21 14:00:57.000000002 +0100 ../slsDetectorServer/ALTERA_PLL.h

6
slsDetectorServers/ctbDetectorServer/gitInfoCtb.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git" #define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "44f0dfc3c00d0dd70a683289dde9a2fcbf1e0449" #define GITREPUUID "050854de36f01379e974005e204b6563ffbc7004"
#define GITAUTH "Dhanya_Thattil" #define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4450 #define GITREV 0x4458
#define GITDATE 0x20190320 #define GITDATE 0x20190321
#define GITBRANCH "refactor" #define GITBRANCH "refactor"

6
slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
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@ -196,15 +196,15 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
FILE_LOG(logINFO, ("\tC%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n", clkIndex, value, pllVCOFreqMhz)); FILE_LOG(logINFO, ("\tC%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n", clkIndex, value, pllVCOFreqMhz));
// calculate output frequency // calculate output frequency
uint32_t total_div = pllVCOFreqMhz / value; float total_div = (float)pllVCOFreqMhz / (float)value;
// assume 50% duty cycle // assume 50% duty cycle
uint32_t low_count = total_div / 2; uint32_t low_count = total_div / 2;
uint32_t high_count = low_count; uint32_t high_count = low_count;
uint32_t odd_division = 0; uint32_t odd_division = 0;
cprintf(RED, "toatldiv:%f\n", total_div);
// odd division // odd division
if (total_div > (2 * low_count)) { if (total_div > (float)(2 * low_count)) {
++high_count; ++high_count;
odd_division = 1; odd_division = 1;
} }