From b8204b757ee88327de47e97ba2ba3213bf488848 Mon Sep 17 00:00:00 2001 From: Martin Mueller Date: Wed, 14 May 2025 17:28:37 +0200 Subject: [PATCH] update xctb reg defs --- .../xilinx_ctbDetectorServer/RegisterDefs.h | 58 +++++++++---------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h b/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h index 9bb687289..b14b3e9dd 100644 --- a/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h +++ b/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h @@ -470,18 +470,18 @@ (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST) #define PATTERN_LOOP_0_ADDR_STP_OFST (16) #define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST) -#define PATTERN_LOOP_0_ITERATION_REG (0xB101) +#define PATTERN_LOOP_0_ITERATION_REG (0xB104) -#define PATTERN_WAIT_0_ADDR_REG (0xB102) +#define PATTERN_WAIT_0_ADDR_REG (0xB108) #define PATTERN_WAIT_0_ADDR_OFST (0) #define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST) -#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB103) +#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB10C) -#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB104) +#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB110) -#define PATTERN_LOOP_1_ADDR_REG (0xB105) +#define PATTERN_LOOP_1_ADDR_REG (0xB114) #define PATTERN_LOOP_1_ADDR_STRT_OFST (0) #define PATTERN_LOOP_1_ADDR_STRT_MSK \ @@ -489,18 +489,18 @@ #define PATTERN_LOOP_1_ADDR_STP_OFST (16) #define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST) -#define PATTERN_LOOP_1_ITERATION_REG (0xB106) +#define PATTERN_LOOP_1_ITERATION_REG (0xB118) -#define PATTERN_WAIT_1_ADDR_REG (0xB107) +#define PATTERN_WAIT_1_ADDR_REG (0xB11C) #define PATTERN_WAIT_1_ADDR_OFST (0) #define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST) -#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB108) +#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB120) -#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB109) +#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB124) -#define PATTERN_LOOP_2_ADDR_REG (0xB10A) +#define PATTERN_LOOP_2_ADDR_REG (0xB128) #define PATTERN_LOOP_2_ADDR_STRT_OFST (0) #define PATTERN_LOOP_2_ADDR_STRT_MSK \ @@ -508,18 +508,18 @@ #define PATTERN_LOOP_2_ADDR_STP_OFST (16) #define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST) -#define PATTERN_LOOP_2_ITERATION_REG (0xB10B) +#define PATTERN_LOOP_2_ITERATION_REG (0xB12C) -#define PATTERN_WAIT_2_ADDR_REG (0xB10C) +#define PATTERN_WAIT_2_ADDR_REG (0xB130) #define PATTERN_WAIT_2_ADDR_OFST (0) #define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST) -#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB10D) +#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB134) -#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB10E) +#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB138) -#define PATTERN_LOOP_3_ADDR_REG (0xB10F) +#define PATTERN_LOOP_3_ADDR_REG (0xB13C) #define PATTERN_LOOP_3_ADDR_STRT_OFST (0) #define PATTERN_LOOP_3_ADDR_STRT_MSK \ @@ -527,18 +527,18 @@ #define PATTERN_LOOP_3_ADDR_STP_OFST (16) #define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST) -#define PATTERN_LOOP_3_ITERATION_REG (0xB110) +#define PATTERN_LOOP_3_ITERATION_REG (0xB140) -#define PATTERN_WAIT_3_ADDR_REG (0xB111) +#define PATTERN_WAIT_3_ADDR_REG (0xB144) #define PATTERN_WAIT_3_ADDR_OFST (0) #define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST) -#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB112) +#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB148) -#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB113) +#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB14C) -#define PATTERN_LOOP_4_ADDR_REG (0xB114) +#define PATTERN_LOOP_4_ADDR_REG (0xB150) #define PATTERN_LOOP_4_ADDR_STRT_OFST (0) #define PATTERN_LOOP_4_ADDR_STRT_MSK \ @@ -546,18 +546,18 @@ #define PATTERN_LOOP_4_ADDR_STP_OFST (16) #define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST) -#define PATTERN_LOOP_4_ITERATION_REG (0xB115) +#define PATTERN_LOOP_4_ITERATION_REG (0xB154) -#define PATTERN_WAIT_4_ADDR_REG (0xB116) +#define PATTERN_WAIT_4_ADDR_REG (0xB158) #define PATTERN_WAIT_4_ADDR_OFST (0) #define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST) -#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB117) +#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB15C) -#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB118) +#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB160) -#define PATTERN_LOOP_5_ADDR_REG (0xB119) +#define PATTERN_LOOP_5_ADDR_REG (0xB164) #define PATTERN_LOOP_5_ADDR_STRT_OFST (0) #define PATTERN_LOOP_5_ADDR_STRT_MSK \ @@ -565,10 +565,10 @@ #define PATTERN_LOOP_5_ADDR_STP_OFST (16) #define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST) -#define PATTERN_LOOP_5_ITERATION_REG (0xB11A) +#define PATTERN_LOOP_5_ITERATION_REG (0xB168) -#define PATTERN_WAIT_5_ADDR_REG (0xB11B) +#define PATTERN_WAIT_5_ADDR_REG (0xB16C) #define PATTERN_WAIT_5_ADDR_OFST (0) #define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST) -#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB11C) -#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB11D) \ No newline at end of file +#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB170) +#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB174) \ No newline at end of file