detectors/slsDetectorPackage
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Merge branch 'developer' into gui

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maliakal_d
2019-06-17 17:41:17 +02:00
parent 326b14737f 5b8e4f6c72
commit b6bba0b7bc
15 changed files with 874 additions and 469 deletions
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3
slsDetectorServers/ctbDetectorServer/Makefile
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@@ -10,7 +10,8 @@ INSTMODE = 0777
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRC_CLNT:.c=.o)
all: clean versioning $(PROGS)
#all: clean versioning $(PROGS)
all: clean $(PROGS)
boot: $(OBJS)

BIN
slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
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30
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@@ -1633,7 +1633,7 @@ void configurePhase(enum CLKINDEX ind, int val, int degrees) {
return;
}
FILE_LOG(logINFO, ("\tConfiguring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
FILE_LOG(logDEBUG1, ("\tConfiguring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
int valShift = val;
// convert to phase shift
if (degrees) {
@@ -1649,6 +1649,7 @@ void configurePhase(enum CLKINDEX ind, int val, int degrees) {
FILE_LOG(logINFO, ("\tNothing to do in Phase Shift\n"));
return;
}
FILE_LOG(logINFOBLUE, ("\tConfiguring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
int phase = 0;
if (relativePhase > 0) {
@@ -1723,15 +1724,32 @@ void configureFrequency(enum CLKINDEX ind, int val) {
return;
}
// reset phase
if (ind == ADC_CLK || ind == DBIT_CLK) {
FILE_LOG(logINFO, ("\tReseting phase of %s\n", clock_names[ind]));
configurePhase(ind, 0, 0);
}
// Remembering adcphase/ dbit phase
int adcPhase = getPhase(ADC_CLK, 0);
FILE_LOG(logDEBUG1, ("\tRemembering ADC phase: %d\n", adcPhase));
int dbitPhase = getPhase(DBIT_CLK, 0);
FILE_LOG(logDEBUG1, ("\tRemembering DBIT phase: %d\n", dbitPhase));
// Calculate and set output frequency
clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));
// adc and dbit phase is reset by pll (when setting output frequency)
clkPhase[ADC_CLK] = 0;
clkPhase[DBIT_CLK] = 0;
// set the phase if custom set
if (clkPhase[ADC_CLK] != adcPhase) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting ADC phase to %d\n", adcPhase));
configurePhase(ADC_CLK, adcPhase, 0);
}
if (clkPhase[DBIT_CLK] != dbitPhase) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting DBIT phase to %d\n", dbitPhase));
configurePhase(DBIT_CLK, dbitPhase, 0);
}
// required to reconfigure as adc clock is stopped temporarily when resetting pll (in changing output frequency)
AD9257_Configure();
}
int getFrequency(enum CLKINDEX ind) {

20
slsDetectorServers/slsDetectorServer/AD9257.h
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@@ -267,21 +267,13 @@ void AD9257_Configure(){
FILE_LOG(logINFO, ("\tPower mode chip run\n"));
AD9257_Set(AD9257_POWER_MODE_REG, AD9257_INT_CHIP_RUN_VAL);
// binary offset
FILE_LOG(logINFO, ("\tBinary offset\n"));
AD9257_Set(AD9257_OUT_MODE_REG, AD9257_OUT_BINARY_OFST_VAL);
// binary offset, lvds-iee reduced
FILE_LOG(logINFO, ("\tBinary offset, Lvds-ieee reduced\n"));
AD9257_Set(AD9257_OUT_MODE_REG, AD9257_OUT_BINARY_OFST_VAL | AD9257_OUT_LVDS_IEEE_VAL);
//output clock phase
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
FILE_LOG(logINFO, ("\tOutput clock phase is at default: 180\n"));
#else
FILE_LOG(logINFO, ("\tOutput clock phase: 60\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_60_VAL);
#endif
// lvds-iee reduced , binary offset
FILE_LOG(logINFO, ("\tLvds-iee reduced, binary offset\n"));
AD9257_Set(AD9257_OUT_MODE_REG, AD9257_OUT_LVDS_IEEE_VAL);
FILE_LOG(logINFO, ("\tOutput clock phase: 180\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_180_VAL);
// all devices on chip to receive next command
FILE_LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
@@ -298,9 +290,7 @@ void AD9257_Configure(){
AD9257_SetVrefVoltage(AD9257_VREF_DEFAULT_VAL, 0);
#else
FILE_LOG(logINFO, ("\tVref 1.33\n"));
//AD9257_Set(AD9257_VREF_REG, AD9257_VREF_1_33_VAL);
AD9257_SetVrefVoltage(AD9257_VREF_1_33_VAL, 0);
#endif
// no test mode

2
slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
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@@ -225,7 +225,7 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
// write frequency (post-scale output counter C)
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val);
// reset required to keep the phase
// reset required to keep the phase (must reconfigure adcs again after this as adc clock is stopped temporarily when resetting pll)
ALTERA_PLL_ResetPLL ();
/*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count));