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updated gotthard2 api etc

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This commit is contained in:
maliakal_d 2019-10-01 16:26:42 +02:00
parent c6fd13e49c
commit b3ff825ce8
5 changed files with 39 additions and 36 deletions
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62
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
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@ -1,10 +1,12 @@
// stuff from Carlos
#pragma once #pragma once
/* Definitions for FPGA*/ /* Definitions for FPGA*/
#define BASE_CONTROL (0x000) #define BASE_CONTROL (0x000)
#define BASE_PATTERN_CONTROL (0x200) #define BASE_ACQUISITION (0x200)
#define BASE_PATTERN_RAM (0x10000) #define BASE_UDP_RAM (0x1000)
/* Module Control Board Serial Number register */
#define MCB_SERIAL_NO_REG (0x00 + BASE_CONTROL)
/* FPGA Version register */ /* FPGA Version register */
#define FPGA_VERSION_REG (0x04 + BASE_CONTROL) #define FPGA_VERSION_REG (0x04 + BASE_CONTROL)
@ -14,55 +16,57 @@
#define DETECTOR_TYPE_OFST (24) #define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST) #define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* Module Control Board Serial Number register TODO: versionnumber and serial number? */ /* API Version register */
#define MCB_SERIAL_NO_REG (0x00 + BASE_CONTROL)
/* API Version register TODO: MSK and ofst? */
#define API_VERSION_REG (0x08 + BASE_CONTROL) #define API_VERSION_REG (0x08 + BASE_CONTROL)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
/* Fix pattern register */ /* Fix pattern register */
#define FIX_PATT_REG (0x0C + BASE_CONTROL) #define FIX_PATT_REG (0x0D + BASE_CONTROL)
#define FIX_PATT_VAL (0xACDC2019) #define FIX_PATT_VAL (0xACDC2019)
/* Status register */ /* Status register */
#define STATUS_REG (0x10 + BASE_CONTROL) #define STATUS_REG (0x12 + BASE_CONTROL)
// TODO: is this bit implemented (else make it ifdef virtual) #ifdef VIRTUAL
#define RUN_BUSY_OFST (0) #define RUN_BUSY_OFST (0)
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST) #define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
#endif
/* Look at me register TODO: is this a RW register */ /* Look at me register */
#define LOOK_AT_ME_REG (0x14 + BASE_CONTROL) //Not used in firmware or software, good to play with #define LOOK_AT_ME_REG (0x16 + BASE_CONTROL)
/* Pattern Control FPGA registers --------------------------------------------------*/ /* Pattern Control FPGA registers TODO --------------------------------------------------*/
//TODO: do we really need the get delay and get period?
/* Cycles left 64bit Register */ /* Cycles left 64bit Register */
#define GET_CYCLES_LSB_REG (0x10 + BASE_PATTERN_CONTROL) #define GET_CYCLES_LSB_REG (0x10 + BASE_ACQUISITION)
#define GET_CYCLES_MSB_REG (0x14 + BASE_PATTERN_CONTROL) #define GET_CYCLES_MSB_REG (0x14 + BASE_ACQUISITION)
/* Frames left 64bit Register */ /* Frames left 64bit Register */
#define GET_FRAMES_LSB_REG (0x18 + BASE_PATTERN_CONTROL) #define GET_FRAMES_LSB_REG (0x18 + BASE_ACQUISITION)
#define GET_FRAMES_MSB_REG (0x1C + BASE_PATTERN_CONTROL) #define GET_FRAMES_MSB_REG (0x1C + BASE_ACQUISITION)
/* Delay 64bit Write-register */ /* Delay 64bit Write-register */
#define SET_DELAY_LSB_REG (0x88 + BASE_PATTERN_CONTROL) #define SET_DELAY_LSB_REG (0x88 + BASE_ACQUISITION)
#define SET_DELAY_MSB_REG (0x8C + BASE_PATTERN_CONTROL) #define SET_DELAY_MSB_REG (0x8C + BASE_ACQUISITION)
/* Cylces 64bit Write-register */ /* Cylces 64bit Write-register */
#define SET_CYCLES_LSB_REG (0x90 + BASE_PATTERN_CONTROL) #define SET_CYCLES_LSB_REG (0x90 + BASE_ACQUISITION)
#define SET_CYCLES_MSB_REG (0x94 + BASE_PATTERN_CONTROL) #define SET_CYCLES_MSB_REG (0x94 + BASE_ACQUISITION)
/* Frames 64bit Write-register */ /* Frames 64bit Write-register */
#define SET_FRAMES_LSB_REG (0x98 + BASE_PATTERN_CONTROL) #define SET_FRAMES_LSB_REG (0x98 + BASE_ACQUISITION)
#define SET_FRAMES_MSB_REG (0x9C + BASE_PATTERN_CONTROL) #define SET_FRAMES_MSB_REG (0x9C + BASE_ACQUISITION)
/* Period 64bit Write-register */ /* Period 64bit Write-register */
#define SET_PERIOD_LSB_REG (0xA0 + BASE_PATTERN_CONTROL) #define SET_PERIOD_LSB_REG (0xA0 + BASE_ACQUISITION)
#define SET_PERIOD_MSB_REG (0xA4 + BASE_PATTERN_CONTROL) #define SET_PERIOD_MSB_REG (0xA4 + BASE_ACQUISITION)
/* Exptime 64bit Write-register TODO: ?? */ /* Exptime 64bit Write-register */
#define SET_EXPTIME_LSB_REG (0xA8 + BASE_PATTERN_CONTROL) #define SET_EXPTIME_LSB_REG (0xA8 + BASE_ACQUISITION)
#define SET_EXPTIME_MSB_REG (0xBC + BASE_PATTERN_CONTROL) #define SET_EXPTIME_MSB_REG (0xBC + BASE_ACQUISITION)

BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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7
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -193,7 +193,7 @@ int testBus() {
FILE_LOG(logINFO, ("Testing Bus:\n")); FILE_LOG(logINFO, ("Testing Bus:\n"));
int ret = OK; int ret = OK;
u_int32_t addr = LOOK_AT_ME_REG; //TODO: is this a RW register? u_int32_t addr = LOOK_AT_ME_REG;
int times = 1000 * 1000; int times = 1000 * 1000;
int i = 0; int i = 0;
@ -245,7 +245,7 @@ u_int64_t getFirmwareAPIVersion() {
#ifdef VIRTUAL #ifdef VIRTUAL
return 0; return 0;
#endif #endif
return ((bus_r(API_VERSION_REG)));//TODO: & API_VERSION_MSK) >> API_VERSION_OFST); return ((bus_r(API_VERSION_REG) & API_VERSION_MSK) >> API_VERSION_OFST);
} }
u_int32_t getDetectorNumber(){ u_int32_t getDetectorNumber(){
@ -519,7 +519,7 @@ int configureMAC() {
FILE_LOG(logINFO, ("\tDest. Port : %d \t\t\t(0x%08x)\n\n",dstport, dstport)); FILE_LOG(logINFO, ("\tDest. Port : %d \t\t\t(0x%08x)\n\n",dstport, dstport));
// start addr // start addr
uint32_t addr = BASE_PATTERN_RAM; uint32_t addr = BASE_UDP_RAM;
// calculate rxr endpoint offset // calculate rxr endpoint offset
//addr += (iRxEntry * RXR_ENDPOINT_OFST);//TODO: is there round robin already implemented? //addr += (iRxEntry * RXR_ENDPOINT_OFST);//TODO: is there round robin already implemented?
// get struct memory // get struct memory
@ -558,7 +558,6 @@ int configureMAC() {
//TODO? //TODO?
//cleanFifos(); //cleanFifos();
//resetCore(); //resetCore();
//alignDeserializer();
return OK; return OK;
} }

4
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
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@ -1,7 +1,7 @@
#pragma once #pragma once
#include "sls_detector_defs.h" #include "sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN (0x190000)//TODO #define REQRD_FRMWRE_VRSN (0x190000)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000) #define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -9,7 +9,7 @@
#define NCHAN (128) #define NCHAN (128)
#define NCHIP (10) #define NCHIP (10)
#define NDAC (16) #define NDAC (16)
#define DYNAMIC_RANGE (16) //TODO: correct? #define DYNAMIC_RANGE (16)
#define HV_SOFT_MAX_VOLTAGE (200) #define HV_SOFT_MAX_VOLTAGE (200)
#define HV_HARD_MAX_VOLTAGE (530) #define HV_HARD_MAX_VOLTAGE (530)

2
slsSupportLib/include/versionAPI.h
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@ -6,7 +6,7 @@
#define APIMOENCH 0x190820 #define APIMOENCH 0x190820
#define APICTB 0x190930 #define APICTB 0x190930
#define APIGOTTHARD 0x190930 #define APIGOTTHARD 0x190930
#define APIGOTTHARD2 0x190930
#define APIJUNGFRAU 0x190930 #define APIJUNGFRAU 0x190930
#define APIMYTHEN3 0x190930 #define APIMYTHEN3 0x190930
#define APIEIGER 0x190930 #define APIEIGER 0x190930
#define APIGOTTHARD2 0x191001