detectors/slsDetectorPackage
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This commit is contained in:
maliakal_d
2021-10-19 14:49:43 +02:00
parent 3726ae3fd1
commit b39c64032d
66 changed files with 642 additions and 624 deletions
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95
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -296,7 +296,8 @@ int getModuleId(int *ret, char *mess) {
void setModuleId(int modid) {
LOG(logINFOBLUE, ("Setting module id in fpga: %d\n", modid))
bus_w(MOD_ID_REG, bus_r(MOD_ID_REG) & ~MOD_ID_MSK);
bus_w(MOD_ID_REG, bus_r(MOD_ID_REG) | ((modid << MOD_ID_OFST) & MOD_ID_MSK));
bus_w(MOD_ID_REG,
bus_r(MOD_ID_REG) | ((modid << MOD_ID_OFST) & MOD_ID_MSK));
}
u_int64_t getDetectorMAC() {
@ -1915,23 +1916,21 @@ int checkDetectorType() {
int type = atoi(buffer);
if (type > TYPE_NO_MODULE_STARTING_VAL) {
LOG(logERROR,
("No Module attached! Expected %d, %d or %d for Gotthard2, got %d\n",
TYPE_GOTTHARD2_MODULE_VAL,
TYPE_GOTTHARD2_25UM_MASTER_MODULE_VAL,
TYPE_GOTTHARD2_25UM_SLAVE_MODULE_VAL,
type));
("No Module attached! Expected %d, %d or %d for Gotthard2, got "
"%d\n",
TYPE_GOTTHARD2_MODULE_VAL, TYPE_GOTTHARD2_25UM_MASTER_MODULE_VAL,
TYPE_GOTTHARD2_25UM_SLAVE_MODULE_VAL, type));
return -2;
}
if ((abs(type - TYPE_GOTTHARD2_MODULE_VAL) > TYPE_TOLERANCE) &&
(abs(type - TYPE_GOTTHARD2_25UM_MASTER_MODULE_VAL) > TYPE_TOLERANCE) &&
(abs(type - TYPE_GOTTHARD2_25UM_SLAVE_MODULE_VAL) > TYPE_TOLERANCE)) {
(abs(type - TYPE_GOTTHARD2_25UM_MASTER_MODULE_VAL) > TYPE_TOLERANCE) &&
(abs(type - TYPE_GOTTHARD2_25UM_SLAVE_MODULE_VAL) > TYPE_TOLERANCE)) {
LOG(logERROR,
("Wrong Module attached! Expected %d, %d or %d for Gotthard2, got %d\n",
TYPE_GOTTHARD2_MODULE_VAL,
TYPE_GOTTHARD2_25UM_MASTER_MODULE_VAL,
TYPE_GOTTHARD2_25UM_SLAVE_MODULE_VAL,
type));
("Wrong Module attached! Expected %d, %d or %d for Gotthard2, got "
"%d\n",
TYPE_GOTTHARD2_MODULE_VAL, TYPE_GOTTHARD2_25UM_MASTER_MODULE_VAL,
TYPE_GOTTHARD2_25UM_SLAVE_MODULE_VAL, type));
return FAIL;
}
return OK;
@ -2088,52 +2087,52 @@ int getVCOFrequency(enum CLKINDEX ind) {
int setReadoutSpeed(int val) {
switch (val) {
case G2_108MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 108 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_108_CLKDIV_0) == FAIL) {
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_108_CLKDIV_1) == FAIL) {
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_108_CLKPHASE_DEG_1, 1) == FAIL) {
return FAIL;
}
break;
case G2_144MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 144 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_144_CLKDIV_0) == FAIL) {
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_144_CLKDIV_1) == FAIL) {
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_144_CLKPHASE_DEG_1, 1) == FAIL) {
return FAIL;
}
break;
default:
LOG(logERROR, ("Unknown readout speed %d\n", val));
case G2_108MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 108 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_108_CLKDIV_0) == FAIL) {
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_108_CLKDIV_1) == FAIL) {
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_108_CLKPHASE_DEG_1, 1) == FAIL) {
return FAIL;
}
break;
case G2_144MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 144 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_144_CLKDIV_0) == FAIL) {
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_144_CLKDIV_1) == FAIL) {
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_144_CLKPHASE_DEG_1, 1) == FAIL) {
return FAIL;
}
break;
default:
LOG(logERROR, ("Unknown readout speed %d\n", val));
return FAIL;
}
return OK;
}
int getReadoutSpeed(int* retval) {
//TODO ASIC and ADIFreg need to check????
// clkdiv 2, 3, 4, 5?
int getReadoutSpeed(int *retval) {
// TODO ASIC and ADIFreg need to check????
// clkdiv 2, 3, 4, 5?
if (clkDivider[READOUT_C0] == SPEED_108_CLKDIV_0 &&
clkDivider[READOUT_C1] == SPEED_108_CLKDIV_1 &&
getPhase(READOUT_C1, 1) == SPEED_108_CLKPHASE_DEG_1) {
clkDivider[READOUT_C1] == SPEED_108_CLKDIV_1 &&
getPhase(READOUT_C1, 1) == SPEED_108_CLKPHASE_DEG_1) {
*retval = G2_108MHZ;
}
else if (clkDivider[READOUT_C0] == SPEED_144_CLKDIV_0 &&
clkDivider[READOUT_C1] == SPEED_144_CLKDIV_1 &&
getPhase(READOUT_C1, 1) == SPEED_144_CLKPHASE_DEG_1) {
clkDivider[READOUT_C1] == SPEED_144_CLKDIV_1 &&
getPhase(READOUT_C1, 1) == SPEED_144_CLKPHASE_DEG_1) {
*retval = G2_144MHZ;
}
else {
*retval = -1;
return FAIL;
@ -2154,7 +2153,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
char *clock_names[] = {CLK_NAMES};
LOG(logINFOBLUE, ("Setting %s clock (%d) divider from %d to %d\n",
clock_names[ind], ind, clkDivider[ind], val));
clock_names[ind], ind, clkDivider[ind], val));
// Remembering old phases in degrees
int oldPhases[NUM_CLOCKS];