diff --git a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer index 273a5dbb0..4debfad3e 100755 Binary files a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer and b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer differ diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c index bf9eff71f..854011305 100644 --- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c @@ -44,8 +44,8 @@ int virtual_stop = 0; enum detectorSettings thisSettings = UNINITIALIZED; int32_t clkPhase[NUM_CLOCKS] = {}; -uint32_t clkFrequency[NUM_CLOCKS] = {}; -uint32_t systemFrequency = 0; +uint32_t clkDivider[NUM_CLOCKS] = {}; +double systemFrequency = 0; int highvoltage = 0; int dacValues[NDAC] = {}; int onChipdacValues[ONCHIP_NDAC][NCHIP] = {}; @@ -353,12 +353,12 @@ void initStopServer() { void setupDetector() { LOG(logINFO, ("This Server is for 1 Gotthard2 module \n")); - clkFrequency[READOUT_C0] = DEFAULT_READOUT_C0; - clkFrequency[READOUT_C1] = DEFAULT_READOUT_C1; - clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0; - clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1; - clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2; - clkFrequency[SYSTEM_C3] = DEFAULT_SYSTEM_C3; + clkDivider[READOUT_C0] = DEFAULT_READOUT_C0; + clkDivider[READOUT_C1] = DEFAULT_READOUT_C1; + clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0; + clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1; + clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2; + clkDivider[SYSTEM_C3] = DEFAULT_SYSTEM_C3; systemFrequency = INT_SYSTEM_C0_FREQUENCY; detPos[0] = 0; detPos[1] = 0; @@ -1450,13 +1450,12 @@ int getMaxPhase(enum CLKINDEX ind) { LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind)); return -1; } - int vcofreq = getVCOFrequency(ind); int maxshiftstep = ALTERA_PLL_C10_GetMaxPhaseShiftStepsofVCO(); - int ret = ((double)vcofreq / (double)clkFrequency[ind]) * maxshiftstep; + int ret = clkDivider[ind] * maxshiftstep; char* clock_names[] = {CLK_NAMES}; - LOG(logDEBUG1, ("\tMax Phase Shift (%s): %d (Clock: %d Hz, VCO:%d Hz)\n", - clock_names[ind], ret, clkFrequency[ind], vcofreq)); + LOG(logDEBUG1, ("\tMax Phase Shift (%s): %d (Clock Div: %d)\n", + clock_names[ind], ret, clkDivider[ind])); return ret; } @@ -1489,7 +1488,7 @@ int getFrequency(enum CLKINDEX ind) { LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind)); return -1; } - return clkFrequency[ind]; + return (((double)getVCOFrequency(ind) / (double)clkDivider[ind]) + 0.5); } int getVCOFrequency(enum CLKINDEX ind) { @@ -1514,28 +1513,28 @@ int setClockDivider(enum CLKINDEX ind, int val) { return FAIL; } char* clock_names[] = {CLK_NAMES}; - int vcofreq = getVCOFrequency(ind); - int currentdiv = vcofreq / (int)clkFrequency[ind]; - int newfreq = vcofreq / val; - LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq)); + LOG(logINFO, ("\tSetting %s clock (%d) divider from %d to %d\n", + clock_names[ind], ind, clkDivider[ind], val)); // Remembering old phases in degrees int oldPhases[NUM_CLOCKS]; { int i = 0; for (i = 0; i < NUM_CLOCKS; ++i) { - oldPhases [i] = getPhase(i, 1); - LOG(logDEBUG1, ("\tRemembering %s clock (%d) phase: %d degrees\n", clock_names[ind], ind, oldPhases[i])); + oldPhases[i] = getPhase(i, 1); + LOG(logDEBUG1, ("\tRemembering %s clock (%d) phase: %d degrees\n", + clock_names[ind], ind, oldPhases[i])); } } // Calculate and set output frequency int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL); int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind); - ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq); - clkFrequency[ind] = newfreq; - LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind])); + ALTERA_PLL_C10_SetOuputClockDivider (pllIndex, clkIndex, val); + clkDivider[ind] = val; + LOG(logINFO, ("\t%s clock (%d) divider set to %d\n", + clock_names[ind], ind, clkDivider[ind])); // update system frequency if (ind == SYSTEM_C0) { setTimingSource(getTimingSource()); @@ -1558,7 +1557,8 @@ int setClockDivider(enum CLKINDEX ind, int val) { for (i = 0; i < NUM_CLOCKS; ++i) { int currPhaseDeg = getPhase(i, 1); if (oldPhases[i] != currPhaseDeg) { - LOG(logINFO, ("\tCorrecting %s clock (%d) phase from %d to %d degrees\n", clock_names[i], i, currPhaseDeg, oldPhases[i])); + LOG(logINFO, ("\tCorrecting %s clock (%d) phase from %d to %d degrees\n", + clock_names[i], i, currPhaseDeg, oldPhases[i])); setPhase(i, oldPhases[i], 1); } } @@ -1571,7 +1571,7 @@ int getClockDivider(enum CLKINDEX ind) { LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind)); return -1; } - return (getVCOFrequency(ind) / (int)clkFrequency[ind]); + return clkDivider[ind]; } int setInjectChannel(int offset, int increment) { @@ -1991,7 +1991,7 @@ void setTimingSource(enum timingSourceType value) { case TIMING_EXTERNAL: LOG(logINFO, ("Setting timing source to exernal\n")); bus_w(addr, (bus_r(addr) | CONTROL_TIMING_SOURCE_EXT_MSK)); - systemFrequency = clkFrequency[SYSTEM_C0]; + systemFrequency = ((double)getVCOFrequency(SYSTEM_C0) / (double)clkDivider[SYSTEM_C0]); break; default: LOG(logERROR, ("Unknown timing source %d\n", value)); diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h index 27ad9568f..d0067deb0 100644 --- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h +++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h @@ -44,12 +44,12 @@ #define DEFAULT_CURRENT_SOURCE (0) #define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL) -#define DEFAULT_READOUT_C0 (144444448) // rdo_clk, 144 MHz -#define DEFAULT_READOUT_C1 (144444448) // rdo_x2_clk, 144 MHz -#define DEFAULT_SYSTEM_C0 (144444448) // run_clk, 144 MHz -#define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz -#define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz -#define DEFAULT_SYSTEM_C3 (144444448) // str_clk, 144 MHz +#define DEFAULT_READOUT_C0 (6)//(144444448) // rdo_clk, 144 MHz +#define DEFAULT_READOUT_C1 (6)//(144444448) // rdo_x2_clk, 144 MHz +#define DEFAULT_SYSTEM_C0 (5)//(144444448) // run_clk, 144 MHz +#define DEFAULT_SYSTEM_C1 (10)//(72222224) // chip_clk, 72 MHz +#define DEFAULT_SYSTEM_C2 (40)//(18055556) // sync_clk, 18 MHz +#define DEFAULT_SYSTEM_C3 (5)//(144444448) // str_clk, 144 MHz /* Firmware Definitions */ #define IP_HEADER_SIZE (20) diff --git a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer index a498fca68..9fd407e77 100755 Binary files a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer and b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer differ diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c index f34f6c124..f5f16d533 100644 --- a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c @@ -40,7 +40,7 @@ int virtual_stop = 0; #endif int32_t clkPhase[NUM_CLOCKS] = {}; -uint32_t clkFrequency[NUM_CLOCKS] = {}; +uint32_t clkDivider[NUM_CLOCKS] = {}; int highvoltage = 0; int dacValues[NDAC] = {}; @@ -340,11 +340,11 @@ void initStopServer() { void setupDetector() { LOG(logINFO, ("This Server is for 1 Mythen3 module \n")); - clkFrequency[READOUT_C0] = DEFAULT_READOUT_C0; - clkFrequency[READOUT_C1] = DEFAULT_READOUT_C1; - clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0; - clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1; - clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2; + clkDivider[READOUT_C0] = DEFAULT_READOUT_C0; + clkDivider[READOUT_C1] = DEFAULT_READOUT_C1; + clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0; + clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1; + clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2; highvoltage = 0; { @@ -509,12 +509,12 @@ int setExpTime(int64_t val) { return FAIL; } LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val)); - val *= (1E-9 * clkFrequency[SYSTEM_C0]); + val *= (1E-9 * getFrequency(SYSTEM_C0)); setPatternWaitTime(0, val); // validate for tolerance int64_t retval = getExpTime(); - val /= (1E-9 * clkFrequency[SYSTEM_C0]); + val /= (1E-9 * getFrequency(SYSTEM_C0)); if (val != retval) { return FAIL; } @@ -522,7 +522,7 @@ int setExpTime(int64_t val) { } int64_t getExpTime() { - return setPatternWaitTime(0, -1) / (1E-9 * clkFrequency[SYSTEM_C0]); + return setPatternWaitTime(0, -1) / (1E-9 * getFrequency(SYSTEM_C0)); } int setPeriod(int64_t val) { @@ -1236,13 +1236,12 @@ int getMaxPhase(enum CLKINDEX ind) { LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind)); return -1; } - int vcofreq = getVCOFrequency(ind); int maxshiftstep = ALTERA_PLL_C10_GetMaxPhaseShiftStepsofVCO(); - int ret = ((double)vcofreq / (double)clkFrequency[ind]) * maxshiftstep; + int ret = clkDivider[ind] * maxshiftstep; char* clock_names[] = {CLK_NAMES}; - LOG(logDEBUG1, ("\tMax Phase Shift (%s): %d (Clock: %d Hz, VCO:%d Hz)\n", - clock_names[ind], ret, clkFrequency[ind], vcofreq)); + LOG(logDEBUG1, ("\tMax Phase Shift (%s): %d (Clock Div: %d)\n", + clock_names[ind], ret, clkDivider[ind])); return ret; } @@ -1275,7 +1274,7 @@ int getFrequency(enum CLKINDEX ind) { LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind)); return -1; } - return clkFrequency[ind]; + return (getVCOFrequency(ind) / clkDivider[ind]); } int getVCOFrequency(enum CLKINDEX ind) { @@ -1300,27 +1299,28 @@ int setClockDivider(enum CLKINDEX ind, int val) { return FAIL; } char* clock_names[] = {CLK_NAMES}; - int vcofreq = getVCOFrequency(ind); - int currentdiv = vcofreq / (int)clkFrequency[ind]; - int newfreq = vcofreq / val; - LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq)); + LOG(logINFO, ("\tSetting %s clock (%d) divider from %d to %d\n", + clock_names[ind], ind, clkDivider[ind], val)); // Remembering old phases in degrees int oldPhases[NUM_CLOCKS]; { int i = 0; for (i = 0; i < NUM_CLOCKS; ++i) { - oldPhases [i] = getPhase(i, 1); + oldPhases[i] = getPhase(i, 1); + LOG(logDEBUG1, ("\tRemembering %s clock (%d) phase: %d degrees\n", + clock_names[ind], ind, oldPhases[i])); } } // Calculate and set output frequency int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL); int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind); - ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq); - clkFrequency[ind] = newfreq; - LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind])); + ALTERA_PLL_C10_SetOuputClockDivider (pllIndex, clkIndex, val); + clkDivider[ind] = val; + LOG(logINFO, ("\t%s clock (%d) divider set to %d\n", + clock_names[ind], ind, clkDivider[ind])); // phase is reset by pll (when setting output frequency) if (ind >= READOUT_C0) { @@ -1338,7 +1338,8 @@ int setClockDivider(enum CLKINDEX ind, int val) { for (i = 0; i < NUM_CLOCKS; ++i) { int currPhaseDeg = getPhase(i, 1); if (oldPhases[i] != currPhaseDeg) { - LOG(logINFO, ("\tCorrecting %s clock (%d) phase from %d to %d degrees\n", clock_names[i], i, currPhaseDeg, oldPhases[i])); + LOG(logINFO, ("\tCorrecting %s clock (%d) phase from %d to %d degrees\n", + clock_names[i], i, currPhaseDeg, oldPhases[i])); setPhase(i, oldPhases[i], 1); } } @@ -1351,7 +1352,7 @@ int getClockDivider(enum CLKINDEX ind) { LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind)); return -1; } - return (getVCOFrequency(ind) / (int)clkFrequency[ind]); + return clkDivider[ind]; } /* aquisition */ diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h b/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h index 0486b21af..d584dd268 100644 --- a/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h +++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h @@ -32,11 +32,11 @@ #define DEFAULT_DELAY_AFTER_TRIGGER (0) #define DEFAULT_HIGH_VOLTAGE (0) #define DEFAULT_TIMING_MODE (AUTO_TIMING) -#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz -#define DEFAULT_READOUT_C1 (125000000) // rdo_x2_clk, 125 MHz -#define DEFAULT_SYSTEM_C0 (250000000) // run_clk, 250 MHz -#define DEFAULT_SYSTEM_C1 (125000000) // chip_clk, 125 MHz -#define DEFAULT_SYSTEM_C2 (125000000) // sync_clk, 125 MHz +#define DEFAULT_READOUT_C0 (10)//(125000000) // rdo_clk, 125 MHz +#define DEFAULT_READOUT_C1 (10)//(125000000) // rdo_x2_clk, 125 MHz +#define DEFAULT_SYSTEM_C0 (5)//(250000000) // run_clk, 250 MHz +#define DEFAULT_SYSTEM_C1 (10)//(125000000) // chip_clk, 125 MHz +#define DEFAULT_SYSTEM_C2 (10)//(125000000) // sync_clk, 125 MHz /* Firmware Definitions */ diff --git a/slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h b/slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h index b47d3f080..647fc8b87 100755 --- a/slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h +++ b/slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h @@ -59,7 +59,7 @@ void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos * Calculate and write output frequency * @param pllIndex pll index * @param clkIndex clock index - * @param value frequency in Hz to set to + * @param value clock divider to set to */ -void ALTERA_PLL_C10_SetOuputFrequency (int pllIndex, int clkIndex, int value); +void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value); diff --git a/slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c b/slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c index 996023cb3..518bc9924 100755 --- a/slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c +++ b/slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c @@ -113,21 +113,16 @@ void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos } } - -void ALTERA_PLL_C10_SetOuputFrequency (int pllIndex, int clkIndex, int value) { - int pllVCOFreqHz = ALTERA_PLL_C10_VCO_FREQ[pllIndex]; - LOG(logDEBUG1, ("\tC%d: Setting output frequency for pll %d to %d (pllvcofreq: %dHz)\n", clkIndex, pllIndex, value, pllVCOFreqHz)); - - // calculate output frequency - float total_div = (float)pllVCOFreqHz / (float)value; +void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value) { + LOG(logDEBUG1, ("\tC%d: Setting output clock divider for pll%d to %d\n", clkIndex, pllIndex, value)); // assume 50% duty cycle - uint32_t low_count = total_div / 2; + uint32_t low_count = value / 2; uint32_t high_count = low_count; uint32_t odd_division = 0; // odd division - if (total_div > (float)(2 * low_count)) { + if (value > (int)(2 * low_count)) { ++high_count; odd_division = 1; } @@ -146,7 +141,5 @@ void ALTERA_PLL_C10_SetOuputFrequency (int pllIndex, int clkIndex, int value) { ALTERA_PLL_C10_Reconfigure(pllIndex); // reset required to keep the phase relationships - ALTERA_PLL_C10_ResetPLL (pllIndex); + ALTERA_PLL_C10_ResetPLL (pllIndex); } - - diff --git a/slsSupportLib/include/versionAPI.h b/slsSupportLib/include/versionAPI.h index b0d2ea1d1..5dd211429 100644 --- a/slsSupportLib/include/versionAPI.h +++ b/slsSupportLib/include/versionAPI.h @@ -6,7 +6,7 @@ #define APIEIGER 0x200409 #define APICTB 0x200409 #define APIGOTTHARD 0x200409 -#define APIGOTTHARD2 0x200409 #define APIJUNGFRAU 0x200409 -#define APIMYTHEN3 0x200409 #define APIMOENCH 0x200409 +#define APIMYTHEN3 0x200428 +#define APIGOTTHARD2 0x200428