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m3:smp_clk (timing rxr) changed back to clk div 5

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maliakal_d
2020-09-09 15:55:13 +02:00
parent 97687f0f6d
commit a9d1a78662
3 changed files with 3 additions and 3 deletions
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4
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -42,8 +42,8 @@
#define DEFAULT_SYSTEM_C0 (20) // (50000000) // run_clk, 50 MHz
#define DEFAULT_SYSTEM_C1 (10) //(100000000) // sync_clk, 100 MHz
#define DEFAULT_SYSTEM_C2 (10) //(100000000) // str_clk, 100 MHz
#define DEFAULT_SYSTEM_C3 (10) //(100000000) // smp_clk, 100 MHz
// (DEFAULT_SYSTEM_C3 only for timing receiver)
#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz
// (DEFAULT_SYSTEM_C3 only for timing receiver) should not be changed
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)