detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-06-23 01:58:00 +02:00
Code Issues Actions Packages Releases Activity

merge resolved

Browse Source
This commit is contained in:
maliakal_d
2019-08-21 14:25:21 +02:00
parent 4b0fb5029f 5c393e6204
commit a98271f0c2
31 changed files with 600 additions and 207 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
slsDetectorServers/ctbDetectorServer/Makefile
View File

@ -13,7 +13,8 @@ INSTMODE = 0777
SRCS = $(main_server)communication_funcs.c $(main_server)slsDetectorServer.c $(main_server)slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRCS:.c=.o)
all: clean versioning $(PROGS)
all: clean versioning $(PROGS)
#all: clean $(PROGS)
boot: $(OBJS)

24
slsDetectorServers/ctbDetectorServer/RegisterDefs.h
View File

@ -364,23 +364,23 @@
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x0000FFFF << PATTERN_CNTRL_ADDR_OFST)
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x0000FFFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x0000FFFF << PATTERN_LIMIT_STP_OFST)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/* Pattern Loop 0 Address RW regiser */
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STP_OFST)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW regiser */
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
@ -389,9 +389,9 @@
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STP_OFST)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 1 Iteration RW regiser */
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
@ -400,9 +400,9 @@
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STP_OFST)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 2 Iteration RW regiser */
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
@ -411,20 +411,20 @@
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_0_ADDR_OFST)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
//FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_1_ADDR_OFST)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW regiser */
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_2_ADDR_OFST)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)

BIN
slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
View File

Binary file not shown.

14
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
View File

@ -2163,8 +2163,9 @@ int startStateMachine(){
FILE_LOG(logINFOGREEN, ("Virtual Acquisition started\n"));
return OK;
#endif
int send_to_10g = enableTenGigabitEthernet(-1);
// 1 giga udp
if (!enableTenGigabitEthernet(-1)) {
if (send_to_10g == 0) {
// create udp socket
if(createUDPSocket(0) != OK) {
return FAIL;
@ -2175,7 +2176,9 @@ int startStateMachine(){
FILE_LOG(logINFOBLUE, ("Starting State Machine\n"));
cleanFifos();
unsetFifoReadStrobes(); // FIXME: unnecessary to write bus_w(dumm, 0) as it is 0 in the beginnig and the strobes are always unset if set
if (send_to_10g == 0) {
unsetFifoReadStrobes(); // FIXME: unnecessary to write bus_w(dumm, 0) as it is 0 in the beginnig and the strobes are always unset if set
}
//start state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_ACQSTN_MSK | CONTROL_STRT_EXPSR_MSK);
@ -2332,14 +2335,13 @@ void readFrame(int *ret, char *mess) {
// frames left to give status
int64_t retval = getTimeLeft(FRAME_NUMBER) + 2;
if ( retval > 1) {
*ret = (int)FAIL;
sprintf(mess,"No data and run stopped: %lld frames left\n",(long long int)retval);
FILE_LOG(logERROR, (mess));
} else {
*ret = (int)OK;
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
}
}
*ret = (int)OK;
}
void unsetFifoReadStrobes() {
@ -2430,12 +2432,12 @@ uint32_t checkDataInFifo() {
uint32_t dataPresent = 0;
if (analogEnable) {
uint32_t analogFifoEmpty = bus_r(FIFO_EMPTY_REG);
FILE_LOG(logDEBUG2, ("Analog Fifo Empty (32 channels): 0x%x\n", analogFifoEmpty));
FILE_LOG(logINFO, ("Analog Fifo Empty (32 channels): 0x%08x\n", analogFifoEmpty));
dataPresent = (~analogFifoEmpty);
}
if (!dataPresent && digitalEnable) {
int digitalFifoEmpty = ((bus_r(FIFO_DIN_STATUS_REG) & FIFO_DIN_STATUS_FIFO_EMPTY_MSK) >> FIFO_DIN_STATUS_FIFO_EMPTY_OFST);
FILE_LOG(logDEBUG2, ("Digital Fifo Empty: %d\n",digitalFifoEmpty));
FILE_LOG(logINFO, ("Digital Fifo Empty: %d\n",digitalFifoEmpty));
dataPresent = (digitalFifoEmpty ? 0 : 1);
}
FILE_LOG(logDEBUG2, ("Data in Fifo :0x%x\n", dataPresent));

10
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
View File

@ -4,7 +4,7 @@
#define MIN_REQRD_VRSN_T_RD_API 0x181130
#define REQRD_FRMWR_VRSN 0x190402
#define REQRD_FRMWR_VRSN 0x190821
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
@ -59,9 +59,9 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK (40)
#define DEFAULT_ADC_CLK (20)
#define DEFAULT_SYNC_CLK (20)
#define DEFAULT_RUN_CLK (200) // 40
#define DEFAULT_ADC_CLK (40) // 20
#define DEFAULT_SYNC_CLK (40) // 20
#define DEFAULT_DBIT_CLK (200)
#define HIGHVOLTAGE_MIN (60)
@ -76,7 +76,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
#define VIO_MIN_MV (1200) // for fpga to function
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x7FFF)
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)