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mythen3 frequency fixes

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This commit is contained in:
maliakal_d
2019-11-07 14:35:13 +01:00
parent 615b3b2557
commit a92d931a8f
4 changed files with 24 additions and 27 deletions
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BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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36
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -33,8 +33,8 @@ int virtual_status = 0;
int virtual_stop = 0; int virtual_stop = 0;
#endif #endif
int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0}; int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0};
uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0}; uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0};
int highvoltage = 0; int highvoltage = 0;
int dacValues[NDAC] = {0}; int dacValues[NDAC] = {0};
@ -338,7 +338,6 @@ void setupDetector() {
clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0; clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0;
clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1; clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1;
clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2; clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2;
clkFrequency[SYSTEM_C3] = DEFAULT_SYSTEM_C3;
highvoltage = 0; highvoltage = 0;
{ {
@ -362,10 +361,9 @@ void setupDetector() {
LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC); LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
#endif #endif
//TODO? resetCore();
//resetCore(); resetPeripheral();
//resetPeripheral(); cleanFifos();
//cleanFifos();
// defaults // defaults
setHighVoltage(DEFAULT_HIGH_VOLTAGE); setHighVoltage(DEFAULT_HIGH_VOLTAGE);
@ -408,7 +406,6 @@ void resetCore() {
#endif #endif
FILE_LOG(logINFO, ("Resetting Core\n")); FILE_LOG(logINFO, ("Resetting Core\n"));
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CRE_RST_MSK); bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CRE_RST_MSK);
usleep(1000 * 1000);
} }
void resetPeripheral() { void resetPeripheral() {
@ -478,12 +475,12 @@ int setPeriod(int64_t val) {
return FAIL; return FAIL;
} }
FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val)); FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
val *= (1E-9 * clkFrequency[SYSTEM_C2]); val *= (1E-9 * FIXED_PLL_FREQUENCY);
set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG); set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
// validate for tolerance // validate for tolerance
int64_t retval = getPeriod(); int64_t retval = getPeriod();
val /= (1E-9 * clkFrequency[SYSTEM_C2]); val /= (1E-9 * FIXED_PLL_FREQUENCY);
if (val != retval) { if (val != retval) {
return FAIL; return FAIL;
} }
@ -491,7 +488,7 @@ int setPeriod(int64_t val) {
} }
int64_t getPeriod() { int64_t getPeriod() {
return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * clkFrequency[SYSTEM_C2]); return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * FIXED_PLL_FREQUENCY);
} }
int setDelayAfterTrigger(int64_t val) { int setDelayAfterTrigger(int64_t val) {
@ -500,12 +497,12 @@ int setDelayAfterTrigger(int64_t val) {
return FAIL; return FAIL;
} }
FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val)); FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
val *= (1E-9 * clkFrequency[SYSTEM_C2]); val *= (1E-9 * FIXED_PLL_FREQUENCY);
set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG); set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
// validate for tolerance // validate for tolerance
int64_t retval = getDelayAfterTrigger(); int64_t retval = getDelayAfterTrigger();
val /= (1E-9 * clkFrequency[SYSTEM_C2]); val /= (1E-9 * FIXED_PLL_FREQUENCY);
if (val != retval) { if (val != retval) {
return FAIL; return FAIL;
} }
@ -513,7 +510,7 @@ int setDelayAfterTrigger(int64_t val) {
} }
int64_t getDelayAfterTrigger() { int64_t getDelayAfterTrigger() {
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]); return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
} }
@ -526,11 +523,11 @@ int64_t getNumTriggersLeft() {
} }
int64_t getDelayAfterTriggerLeft() { int64_t getDelayAfterTriggerLeft() {
return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]); return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
} }
int64_t getPeriodLeft() { int64_t getPeriodLeft() {
return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]); return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
} }
int64_t getFramesFromStart() { int64_t getFramesFromStart() {
@ -538,11 +535,11 @@ int64_t getFramesFromStart() {
} }
int64_t getActualTime() { int64_t getActualTime() {
return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C3]);//TODO which clock return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY * 2);
} }
int64_t getMeasurementTime() { int64_t getMeasurementTime() {
return get64BitReg(START_FRAME_TIME_LSB_REG, START_FRAME_TIME_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C3]);//TODO which clock return get64BitReg(START_FRAME_TIME_LSB_REG, START_FRAME_TIME_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
} }
@ -693,7 +690,7 @@ int configureMAC() {
//TODO? //TODO?
cleanFifos(); cleanFifos();
//resetCore(); resetCore();
//alignDeserializer(); //alignDeserializer();
return OK; return OK;
} }
@ -1127,7 +1124,6 @@ int setClockDivider(enum CLKINDEX ind, int val) {
clkPhase[SYSTEM_C0] = 0; clkPhase[SYSTEM_C0] = 0;
clkPhase[SYSTEM_C1] = 0; clkPhase[SYSTEM_C1] = 0;
clkPhase[SYSTEM_C2] = 0; clkPhase[SYSTEM_C2] = 0;
clkPhase[SYSTEM_C3] = 0;
} }
// set the phase in degreesif custom set // set the phase in degreesif custom set

13
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -25,13 +25,14 @@
#define DEFAULT_HIGH_VOLTAGE (0) #define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz #define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz #define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz
#define DEFAULT_SYSTEM_C0 (125000000) // run_clk, 125 MHz #define DEFAULT_SYSTEM_C0 (250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (80000000) // chip_clk, 80 MHz #define DEFAULT_SYSTEM_C1 (125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (20000000) // sync_clk, 20 MHz #define DEFAULT_SYSTEM_C2 (125000000) // sync_clk, 125 MHz
#define DEFAULT_SYSTEM_C3 (125000000) // str_clk, 125 MHz
/* Firmware Definitions */ /* Firmware Definitions */
#define IP_HEADER_SIZE (20) #define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (750000000) // 750MHz #define READOUT_PLL_VCO_FREQ_HZ (750000000) // 750MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (750000000) // 750MHz #define SYSTEM_PLL_VCO_FREQ_HZ (750000000) // 750MHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit) #define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
@ -60,8 +61,8 @@ enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3
2800, /* vTrim */ \ 2800, /* vTrim */ \
800 /* VdcSh */ \ 800 /* VdcSh */ \
}; };
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS}; enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3" #define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL}; enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
/* Struct Definitions */ /* Struct Definitions */

2
slsSupportLib/include/versionAPI.h
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@ -7,6 +7,6 @@
#define APIGOTTHARD 0x191106 #define APIGOTTHARD 0x191106
#define APICTB 0x191106 #define APICTB 0x191106
#define APIGOTTHARD2 0x191106 #define APIGOTTHARD2 0x191106
#define APIMYTHEN3 0x191106
#define APIJUNGFRAU 0x191106 #define APIJUNGFRAU 0x191106
#define APIEIGER 0x191106 #define APIEIGER 0x191106
#define APIMYTHEN3 0x191107