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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-09 11:30:43 +02:00
mythen3 frequency fixes
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615b3b2557
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@ -33,8 +33,8 @@ int virtual_status = 0;
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int virtual_stop = 0;
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int virtual_stop = 0;
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#endif
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#endif
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int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
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int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0};
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uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
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uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0};
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int highvoltage = 0;
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int highvoltage = 0;
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int dacValues[NDAC] = {0};
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int dacValues[NDAC] = {0};
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@ -338,7 +338,6 @@ void setupDetector() {
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clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0;
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clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0;
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clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1;
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clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1;
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clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2;
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clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2;
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clkFrequency[SYSTEM_C3] = DEFAULT_SYSTEM_C3;
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highvoltage = 0;
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highvoltage = 0;
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{
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{
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@ -362,10 +361,9 @@ void setupDetector() {
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LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
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LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
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#endif
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#endif
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//TODO?
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resetCore();
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//resetCore();
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resetPeripheral();
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//resetPeripheral();
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cleanFifos();
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//cleanFifos();
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// defaults
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// defaults
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setHighVoltage(DEFAULT_HIGH_VOLTAGE);
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setHighVoltage(DEFAULT_HIGH_VOLTAGE);
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@ -408,7 +406,6 @@ void resetCore() {
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#endif
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#endif
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FILE_LOG(logINFO, ("Resetting Core\n"));
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FILE_LOG(logINFO, ("Resetting Core\n"));
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bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CRE_RST_MSK);
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bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CRE_RST_MSK);
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usleep(1000 * 1000);
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}
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}
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void resetPeripheral() {
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void resetPeripheral() {
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@ -478,12 +475,12 @@ int setPeriod(int64_t val) {
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return FAIL;
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return FAIL;
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}
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}
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FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
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FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
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val *= (1E-9 * clkFrequency[SYSTEM_C2]);
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val *= (1E-9 * FIXED_PLL_FREQUENCY);
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set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
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set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
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// validate for tolerance
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// validate for tolerance
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int64_t retval = getPeriod();
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int64_t retval = getPeriod();
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val /= (1E-9 * clkFrequency[SYSTEM_C2]);
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val /= (1E-9 * FIXED_PLL_FREQUENCY);
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if (val != retval) {
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if (val != retval) {
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return FAIL;
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return FAIL;
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}
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}
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@ -491,7 +488,7 @@ int setPeriod(int64_t val) {
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}
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}
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int64_t getPeriod() {
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int64_t getPeriod() {
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return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * clkFrequency[SYSTEM_C2]);
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return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * FIXED_PLL_FREQUENCY);
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}
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}
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int setDelayAfterTrigger(int64_t val) {
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int setDelayAfterTrigger(int64_t val) {
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@ -500,12 +497,12 @@ int setDelayAfterTrigger(int64_t val) {
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return FAIL;
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return FAIL;
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}
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}
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FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
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FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
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val *= (1E-9 * clkFrequency[SYSTEM_C2]);
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val *= (1E-9 * FIXED_PLL_FREQUENCY);
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set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
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set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
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// validate for tolerance
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// validate for tolerance
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int64_t retval = getDelayAfterTrigger();
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int64_t retval = getDelayAfterTrigger();
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val /= (1E-9 * clkFrequency[SYSTEM_C2]);
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val /= (1E-9 * FIXED_PLL_FREQUENCY);
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if (val != retval) {
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if (val != retval) {
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return FAIL;
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return FAIL;
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}
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}
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@ -513,7 +510,7 @@ int setDelayAfterTrigger(int64_t val) {
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}
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}
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int64_t getDelayAfterTrigger() {
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int64_t getDelayAfterTrigger() {
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return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]);
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return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
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}
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}
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@ -526,11 +523,11 @@ int64_t getNumTriggersLeft() {
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}
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}
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int64_t getDelayAfterTriggerLeft() {
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int64_t getDelayAfterTriggerLeft() {
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return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]);
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return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
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}
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}
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int64_t getPeriodLeft() {
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int64_t getPeriodLeft() {
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return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C2]);
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return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
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}
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}
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int64_t getFramesFromStart() {
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int64_t getFramesFromStart() {
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@ -538,11 +535,11 @@ int64_t getFramesFromStart() {
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}
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}
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int64_t getActualTime() {
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int64_t getActualTime() {
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return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C3]);//TODO which clock
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return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY * 2);
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}
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}
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int64_t getMeasurementTime() {
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int64_t getMeasurementTime() {
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return get64BitReg(START_FRAME_TIME_LSB_REG, START_FRAME_TIME_MSB_REG) / (1E-9 * clkFrequency[SYSTEM_C3]);//TODO which clock
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return get64BitReg(START_FRAME_TIME_LSB_REG, START_FRAME_TIME_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
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}
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}
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@ -693,7 +690,7 @@ int configureMAC() {
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//TODO?
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//TODO?
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cleanFifos();
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cleanFifos();
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//resetCore();
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resetCore();
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//alignDeserializer();
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//alignDeserializer();
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return OK;
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return OK;
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}
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}
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@ -1127,7 +1124,6 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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clkPhase[SYSTEM_C0] = 0;
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clkPhase[SYSTEM_C0] = 0;
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clkPhase[SYSTEM_C1] = 0;
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clkPhase[SYSTEM_C1] = 0;
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clkPhase[SYSTEM_C2] = 0;
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clkPhase[SYSTEM_C2] = 0;
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clkPhase[SYSTEM_C3] = 0;
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}
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}
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// set the phase in degreesif custom set
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// set the phase in degreesif custom set
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@ -25,13 +25,14 @@
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz
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#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz
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#define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz
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#define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz
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#define DEFAULT_SYSTEM_C0 (125000000) // run_clk, 125 MHz
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#define DEFAULT_SYSTEM_C0 (250000000) // run_clk, 250 MHz
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#define DEFAULT_SYSTEM_C1 (80000000) // chip_clk, 80 MHz
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#define DEFAULT_SYSTEM_C1 (125000000) // chip_clk, 125 MHz
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#define DEFAULT_SYSTEM_C2 (20000000) // sync_clk, 20 MHz
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#define DEFAULT_SYSTEM_C2 (125000000) // sync_clk, 125 MHz
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#define DEFAULT_SYSTEM_C3 (125000000) // str_clk, 125 MHz
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/* Firmware Definitions */
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/* Firmware Definitions */
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#define IP_HEADER_SIZE (20)
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#define IP_HEADER_SIZE (20)
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#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
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#define READOUT_PLL_VCO_FREQ_HZ (750000000) // 750MHz
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#define READOUT_PLL_VCO_FREQ_HZ (750000000) // 750MHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (750000000) // 750MHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (750000000) // 750MHz
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#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
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#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
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@ -60,8 +61,8 @@ enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3
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2800, /* vTrim */ \
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2800, /* vTrim */ \
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800 /* VdcSh */ \
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800 /* VdcSh */ \
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};
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};
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enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
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enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
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#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
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#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
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enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
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enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
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/* Struct Definitions */
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/* Struct Definitions */
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@ -7,6 +7,6 @@
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#define APIGOTTHARD 0x191106
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#define APIGOTTHARD 0x191106
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#define APICTB 0x191106
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#define APICTB 0x191106
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#define APIGOTTHARD2 0x191106
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#define APIGOTTHARD2 0x191106
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#define APIMYTHEN3 0x191106
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#define APIJUNGFRAU 0x191106
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#define APIJUNGFRAU 0x191106
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#define APIEIGER 0x191106
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#define APIEIGER 0x191106
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#define APIMYTHEN3 0x191107
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