mythen3 frequency fixes

This commit is contained in:
2019-11-07 14:35:13 +01:00
parent 615b3b2557
commit a92d931a8f
4 changed files with 24 additions and 27 deletions

View File

@ -25,13 +25,14 @@
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz
#define DEFAULT_SYSTEM_C0 (125000000) // run_clk, 125 MHz
#define DEFAULT_SYSTEM_C1 (80000000) // chip_clk, 80 MHz
#define DEFAULT_SYSTEM_C2 (20000000) // sync_clk, 20 MHz
#define DEFAULT_SYSTEM_C3 (125000000) // str_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (125000000) // sync_clk, 125 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (750000000) // 750MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (750000000) // 750MHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
@ -60,8 +61,8 @@ enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3
2800, /* vTrim */ \
800 /* VdcSh */ \
};
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
/* Struct Definitions */