M3clk (#548)

* m3: clock update, cannot set clk 4 and 5 anymore
* updated firmware version

RELEASE.txt

@@ -98,6 +98,7 @@ This document describes the differences between v7.0.0 and v6.x.x
 - ctb and moench Fw fixed (to work with pattern commdand) )addreess length
 - setting rx_hostname (or udp_dstip with rx_hostname not none) will always set udp_dstmac. solves problem of chaing udp_dstip and udp_dstmac stays the same
 - jungfrau reset core and usleep removed (fix for 6.1.1 is now fixed in firmware)
+- m3 clock update, m3 clk 4 and 5 cannot be set
 - g2 change clkdivs 2 3 4 to defaults for burst and cw mode.
 - ctb and moench: allowing 1g non blocking acquire to send data
 - m3 and g2 rr

slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c

@@ -441,7 +441,6 @@ void setupDetector() {
     clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0;
     clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1;
     clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2;
-    clkDivider[SYSTEM_C3] = DEFAULT_SYSTEM_C3;
 
     highvoltage = 0;
     trimmingPrint = logINFO;
@@ -2297,6 +2296,12 @@ int getVCOFrequency(enum CLKINDEX ind) {
 int getMaxClockDivider() { return ALTERA_PLL_C10_GetMaxClockDivider(); }
 
 int setClockDivider(enum CLKINDEX ind, int val) {
+    char *clock_names[] = {CLK_NAMES};
+    if (ind == SYSTEM_C1 || ind == SYSTEM_C2) {
+        LOG(logERROR, ("Cannot set %s and %s for this detector\n",
+                       clock_names[SYSTEM_C1], clock_names[SYSTEM_C2]));
+        return FAIL;
+    }
     return setClockDividerWithTimeUpdateOption(ind, val, 1);
 }
 
@@ -2364,7 +2369,6 @@ int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val,
         clkPhase[SYSTEM_C0] = 0;
         clkPhase[SYSTEM_C1] = 0;
         clkPhase[SYSTEM_C2] = 0;
-        clkPhase[SYSTEM_C3] = 0;
     }
 
     // set the phase in degrees (reset by pll)

slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h

@@ -3,7 +3,7 @@
 #pragma once
 #include "sls/sls_detector_defs.h"
 
-#define REQRD_FRMWRE_VRSN (0x210910)
+#define REQRD_FRMWRE_VRSN (0x220824)
 #define KERNEL_DATE_VRSN  "Mon May 10 18:00:21 CEST 2021"
 #define ID_FILE           "detid_mythen3.txt"
 
@@ -52,13 +52,11 @@
 #define DEFAULT_TRIMBIT_VALUE            (0)
 #define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
 
-#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
+#define DEFAULT_READOUT_C0          (12) //(083333333) // rdo_clk, 83.33 MHz
-#define DEFAULT_READOUT_C1 (10) //(100000000) // smp sample clk (x2), 100 MHz
+#define DEFAULT_READOUT_C1          (12) //(083333333) // rdo_smp_clk, 83.33 MHz
-#define DEFAULT_SYSTEM_C0  (10) //(100000000) // run_clk, 100 MHz
+#define DEFAULT_SYSTEM_C0           (20) //(050000000) // run_clk, 20 MHz
-#define DEFAULT_SYSTEM_C1  (10) //(100000000) // sync_clk, 100 MHz
+#define DEFAULT_SYSTEM_C1           (8)  //(125000000) // str_clk, 125 MHz const
-#define DEFAULT_SYSTEM_C2  (10) //(100000000) // str_clk, 100 MHz
+#define DEFAULT_SYSTEM_C2           (5)  //(200000000) // smp_clk, 200 MHz const
-#define DEFAULT_SYSTEM_C3  (5)  //(200000000) // smp_clk, 200 MHz
-// (DEFAULT_SYSTEM_C3 only for timing receiver) should not be changed
 #define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
 
 #define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
@@ -140,12 +138,12 @@ enum CLKINDEX {
     SYSTEM_C0,
     SYSTEM_C1,
     SYSTEM_C2,
-    SYSTEM_C3,
     NUM_CLOCKS
 };
+#define NUM_CLOCKS_TO_SET (3)
+
 #define CLK_NAMES                                                              \
-    "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2",         \
+    "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
-        "SYSTEM_C3"
 enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
 
 /* Struct Definitions */

slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c

@@ -6017,7 +6017,11 @@ int set_clock_divider(int file_des) {
     // only set
     if (Server_VerifyLock() == OK) {
 
+#ifdef MYTHEN3D
+        if (args[0] >= NUM_CLOCKS_TO_SET) {
+#else
         if (args[0] >= NUM_CLOCKS) {
+#endif
             modeNotImplemented("clock index (divider set)", args[0]);
         }
 
@@ -6075,7 +6079,7 @@ int get_clock_divider(int file_des) {
 #else
     // get only
     if (arg >= NUM_CLOCKS) {
-        modeNotImplemented("clock index (divider set)", arg);
+        modeNotImplemented("clock index (divider get)", arg);
     }
     if (ret == OK) {
         enum CLKINDEX c = (enum CLKINDEX)arg;

slsSupportLib/include/sls/versionAPI.h

@@ -5,11 +5,10 @@
 #define APILIB       0x220609
 #define APIRECEIVER  0x220609
 #define APIGUI       0x220609
-
+#define APICTB       0x221018
-#define APICTB 0x221018
+#define APIGOTTHARD  0x221018
-#define APIGOTTHARD 0x221018
 #define APIGOTTHARD2 0x221018
-#define APIJUNGFRAU 0x221018
+#define APIJUNGFRAU  0x221018
-#define APIMYTHEN3 0x221018
+#define APIMOENCH    0x221018
-#define APIMOENCH 0x221018
+#define APIEIGER     0x221018
-#define APIEIGER 0x221018
+#define APIMYTHEN3 0x221107