From 9c2367e6579f0a8faf34c486f06b81b4f051db34 Mon Sep 17 00:00:00 2001 From: Martin Mueller Date: Fri, 14 Mar 2025 11:45:35 +0100 Subject: [PATCH] update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout --- .../ctbDetectorServer/RegisterDefs.h | 61 +++++++------------ 1 file changed, 23 insertions(+), 38 deletions(-) diff --git a/slsDetectorServers/ctbDetectorServer/RegisterDefs.h b/slsDetectorServers/ctbDetectorServer/RegisterDefs.h index cd525124a..e53c78d6e 100644 --- a/slsDetectorServers/ctbDetectorServer/RegisterDefs.h +++ b/slsDetectorServers/ctbDetectorServer/RegisterDefs.h @@ -198,12 +198,35 @@ #define FIFO_TIN_STATUS_FIFO_EMPTY_4_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST) #define FIFO_TIN_STATUS_FIFO_EMPTY_ALL_MSK (0x0000000F << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST) +/* FIFO Transceiver Fill level RO register */ +#define FIFO_TIN_FILL_REG (0x45 << MEM_MAP_SHIFT) +#define FIFO_TIN_FILL_FIFO_1_OFST (0) +#define FIFO_TIN_FILL_FIFO_1_MSK (0x000001FF << FIFO_TIN_FILL_FIFO__1_OFST) +#define FIFO_TIN_FILL_FIFO_2_OFST (16) +#define FIFO_TIN_FILL_FIFO_2_MSK (0x000001FF << FIFO_TIN_FILL_FIFO__2_OFST) + +/* FIFO ADC Fill level RO register */ +#define FIFO_ADC_FILL_REG (0x46 << MEM_MAP_SHIFT) +#define FIFO_ADC_FILL_FIFO_OFST (0) +#define FIFO_ADC_FILL_FIFO_MSK (0x000001FF << FIFO_ADC_FILL_FIFO_OFST) + +/* Enable continuos readout register */ +#define CONTINUOUS_RO_ENABLE_REG (0x47 << MEM_MAP_SHIFT) +#define CONTINUOUS_RO_ADC_ENABLE_OFST (0) +#define CONTINUOUS_RO_TIN_ENABLE_OFST (1) +#define CONTINUOUS_RO_DBIT_ENABLE_OFST (2) +#define CONTINUOUS_RO_ADC_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_ADC_ENABLE_OFST) +#define CONTINUOUS_RO_TIN_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_TIN_ENABLE_OFST) +#define CONTINUOUS_RO_DBIT_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_DBIT_ENABLE_OFST) + /* FIFO Transceiver In 64 bit RO register */ #define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT) #define FIFO_TIN_MSB_REG (0x32 << MEM_MAP_SHIFT) /* FIFO Digital In Status RO register */ #define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT) +#define FIFO_DIN_STATUS_FIFO_FILL_OFST (0) +#define FIFO_DIN_STATUS_FIFO_FILL_MSK (0x00001FFF) #define FIFO_DIN_STATUS_FIFO_FULL_OFST (30) #define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST) #define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31) @@ -273,44 +296,6 @@ #define DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST (14) #define DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST) -/* Receiver IP Address RW register */ -#define RX_IP_REG (0x45 << MEM_MAP_SHIFT) - -/* UDP Port RW register */ -#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT) - -#define UDP_PORT_RX_OFST (0) -#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST) -#define UDP_PORT_TX_OFST (16) -#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST) - -/* Receiver Mac Address 64 bit RW register */ -#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT) -#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT) - -#define RX_MAC_LSB_OFST (0) -#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST) -#define RX_MAC_MSB_OFST (0) -#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST) - -/* Detector/ Transmitter Mac Address 64 bit RW register */ -#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT) -#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT) - -#define TX_MAC_LSB_OFST (0) -#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST) -#define TX_MAC_MSB_OFST (0) -#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST) - -/* Detector/ Transmitter IP Address RW register */ -#define TX_IP_REG (0x4B << MEM_MAP_SHIFT) - -/* Detector/ Transmitter IP Checksum RW register */ -#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT) - -#define TX_IP_CHECKSUM_OFST (0) -#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST) - /* Configuration RW register */ #define CONFIG_REG (0x4D << MEM_MAP_SHIFT)