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start/stop statemachine for my3 (#68)

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* start/stop statemachine for my3

* runStatus, readFrame, runBusy (use CONTROL_REG) for mythen3

* registers for Pavel

* change dac names Mythen3
This commit is contained in:
Marie Andrä
2019-10-09 13:52:07 +02:00
committed by Dhanya Thattil
parent b109ea8d7d
commit 9b4fc02b0e
5 changed files with 64 additions and 6 deletions
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21
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -45,6 +45,27 @@
/* Look at me register, read only */
#define LOOK_AT_ME_REG (0x005 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with
/* Control RW register */ // assumed for MY3
#define CONTROL_REG (0x021 * REG_OFFSET + BASE_CONTROL)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
#define CONTROL_RN_BSY_OFST (2) // assumed for MY3
#define CONTROL_RN_BSY_MSK (0x00000001 << CONTROL_RN_BSY_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
// #define CONTROL_MMRY_RST_OFST (12)
// #define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (14)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define DTA_OFFSET_REG (0x104 * REG_OFFSET + BASE_CONTROL)
/* Pattern Control FPGA registers --------------------------------------------------*/