jungfrau: new default to asic reg for chipv1.1, filtercells name change, wrongnumberof parameters message change

This commit is contained in:
2021-10-21 11:27:31 +02:00
parent f7a6160e67
commit 9b321d2ee1
5 changed files with 23 additions and 13 deletions

View File

@ -2292,7 +2292,7 @@ class Detector(CppDetectorApi):
@property
@element
def filtercell(self):
def filtercells(self):
"""
[Jungfrau] Set filter capacitor.
Note
@ -2301,8 +2301,8 @@ class Detector(CppDetectorApi):
"""
return self.getFilterCell()
@filtercell.setter
def filtercell(self, value):
@filtercells.setter
def filtercells(self, value):
ut.set_using_dict(self.setFilterCell, value)
@property