detectors/slsDetectorPackage
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maliakal_d 2020-06-16 12:41:39 +02:00
parent efc247f46f
commit 9a80975929
1 changed files with 14 additions and 14 deletions
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12
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
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@ -30,10 +30,10 @@ enum DACINDEX {
E_VISHAPER, E_VISHAPER,
E_VTHRESHOLD E_VTHRESHOLD
}; };
#define DAC_NAMES #define DAC_NAMES \
"VSvP", "Vtrim", "Vrpreamp", "Vrshaper", "VSvN", "Vtgstv", "Vcmp_ll", "Vcmp_lr", "VSvP", "Vtrim", "Vrpreamp", "Vrshaper", "VSvN", "Vtgstv", "Vcmp_ll", \
"Vcal", "Vcmp_rl", "rxb_rb", "rxb_lb", "Vcmp_rr", "Vcp", "Vcn", "Vcmp_lr", "Vcal", "Vcmp_rl", "rxb_rb", "rxb_lb", "Vcmp_rr", "Vcp", \
"Vishaper" "Vcn", "Vishaper"
#define DEFAULT_DAC_VALS \ #define DEFAULT_DAC_VALS \
{ \ { \
0, /* VSvP */ \ 0, /* VSvP */ \
@ -53,7 +53,7 @@ enum DACINDEX {
2000, /* Vcn */ \ 2000, /* Vcn */ \
1550 /* Vishaper */ \ 1550 /* Vishaper */ \
}; };
enum ADCINDEX { enum ADCINDEX {
TEMP_FPGAEXT, TEMP_FPGAEXT,
TEMP_10GE, TEMP_10GE,
TEMP_DCDC, TEMP_DCDC,
@ -62,7 +62,7 @@ enum DACINDEX {
TEMP_FPGA, TEMP_FPGA,
TEMP_FPGAFEBL, TEMP_FPGAFEBL,
TEMP_FPGAFEBR TEMP_FPGAFEBR
}; };
enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G }; enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
enum ROINDEX { E_PARALLEL, E_NON_PARALLEL }; enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
enum CLKINDEX { RUN_CLK, NUM_CLOCKS }; enum CLKINDEX { RUN_CLK, NUM_CLOCKS };