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g2: dbitpipeline

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This commit is contained in:
maliakal_d
2021-08-11 18:01:28 +02:00
parent 7a76064223
commit 9a777b13bb
16 changed files with 258 additions and 211 deletions
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10
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
View File

@ -170,6 +170,16 @@
#define ASIC_CONT_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_ASIC)
#define ASIC_CONT_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_ASIC)
/* ADIF registers --------------------------------------------------*/
/* ADIF Config register */
#define ADIF_CONFIG_REG (0x00 * REG_OFFSET + BASE_ADIF)
#define ADIF_CONFIG_DBIT_PIPELINE_OFST (4)
#define ADIF_CONFIG_DBIT_PIPELINE_MSK (0x00000007 << ADIF_CONFIG_DBIT_PIPELINE_OFST)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */

16
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
View File

@ -1907,6 +1907,22 @@ int powerChip(int on) {
CONTROL_PWR_CHIP_OFST);
}
void setDBITPipeline(int val) {
if (val < 0) {
return;
}
LOG(logINFO, ("Setting dbit pipeline to %d\n", val));
uint32_t addr = ADIF_CONFIG_REG;
bus_w(addr, bus_r(addr) & ~ADIF_CONFIG_DBIT_PIPELINE_MSK);
bus_w(addr, bus_r(addr) | ((val << ADIF_CONFIG_DBIT_PIPELINE_OFST) &
ADIF_CONFIG_DBIT_PIPELINE_MSK));
}
int getDBITPipeline() {
return ((bus_r(ADIF_CONFIG_REG) & ADIF_CONFIG_DBIT_PIPELINE_MSK) >>
ADIF_CONFIG_DBIT_PIPELINE_OFST);
}
int setPhase(enum CLKINDEX ind, int val, int degrees) {
if (ind < 0 || ind >= NUM_CLOCKS) {
LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));