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g2: dbitpipeline

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This commit is contained in:
maliakal_d
2021-08-11 18:01:28 +02:00
parent 7a76064223
commit 9a777b13bb
16 changed files with 258 additions and 211 deletions
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52
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
View File

@ -1840,46 +1840,38 @@ void configureSyncFrequency(enum CLKINDEX ind) {
setFrequency(SYNC_CLK, min);
}
void setPipeline(enum CLKINDEX ind, int val) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
LOG(logERROR, ("Unknown clock index %d to set pipeline\n", ind));
return;
}
void setADCPipeline(int val) {
if (val < 0) {
return;
}
char *clock_names[] = {CLK_NAMES};
LOG(logINFO,
("Setting %s clock (%d) Pipeline to %d\n", clock_names[ind], ind, val));
uint32_t offset = ADC_OFFSET_ADC_PPLN_OFST;
uint32_t mask = ADC_OFFSET_ADC_PPLN_MSK;
if (ind == DBIT_CLK) {
offset = ADC_OFFSET_DBT_PPLN_OFST;
mask = ADC_OFFSET_DBT_PPLN_MSK;
}
LOG(logINFO, ("Setting adc pipeline to %d\n", val));
uint32_t addr = ADC_OFFSET_REG;
// reset value
bus_w(addr, bus_r(addr) & ~mask);
// set value
bus_w(addr, bus_r(addr) | ((val << offset) & mask));
LOG(logDEBUG1,
(" %s clock (%d) Offset: 0x%8x\n", clock_names[ind], ind, bus_r(addr)));
bus_w(addr, bus_r(addr) & ~ADC_OFFSET_ADC_PPLN_MSK);
bus_w(addr, bus_r(addr) | ((val << ADC_OFFSET_ADC_PPLN_OFST) &
ADC_OFFSET_ADC_PPLN_MSK));
}
int getPipeline(enum CLKINDEX ind) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
LOG(logERROR, ("Unknown clock index %d to get pipeline\n", ind));
return -1;
}
if (ind == DBIT_CLK) {
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_DBT_PPLN_MSK) >>
ADC_OFFSET_DBT_PPLN_OFST);
}
int getADCPipeline() {
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_ADC_PPLN_MSK) >>
ADC_OFFSET_ADC_PPLN_OFST);
}
void setDBITPipeline(int val) {
if (val < 0) {
return;
}
LOG(logINFO, ("Setting dbit pipeline to %d\n", val));
uint32_t addr = ADC_OFFSET_REG;
bus_w(addr, bus_r(addr) & ~ADC_OFFSET_DBT_PPLN_MSK);
bus_w(addr, bus_r(addr) | ((val << ADC_OFFSET_DBT_PPLN_OFST) &
ADC_OFFSET_DBT_PPLN_MSK));
}
int getDBITPipeline() {
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_DBT_PPLN_MSK) >>
ADC_OFFSET_DBT_PPLN_OFST);
}
int setLEDEnable(int enable) {
uint32_t addr = CONFIG_REG;

10
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
View File

@ -170,6 +170,16 @@
#define ASIC_CONT_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_ASIC)
#define ASIC_CONT_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_ASIC)
/* ADIF registers --------------------------------------------------*/
/* ADIF Config register */
#define ADIF_CONFIG_REG (0x00 * REG_OFFSET + BASE_ADIF)
#define ADIF_CONFIG_DBIT_PIPELINE_OFST (4)
#define ADIF_CONFIG_DBIT_PIPELINE_MSK (0x00000007 << ADIF_CONFIG_DBIT_PIPELINE_OFST)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */

16
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
View File

@ -1907,6 +1907,22 @@ int powerChip(int on) {
CONTROL_PWR_CHIP_OFST);
}
void setDBITPipeline(int val) {
if (val < 0) {
return;
}
LOG(logINFO, ("Setting dbit pipeline to %d\n", val));
uint32_t addr = ADIF_CONFIG_REG;
bus_w(addr, bus_r(addr) & ~ADIF_CONFIG_DBIT_PIPELINE_MSK);
bus_w(addr, bus_r(addr) | ((val << ADIF_CONFIG_DBIT_PIPELINE_OFST) &
ADIF_CONFIG_DBIT_PIPELINE_MSK));
}
int getDBITPipeline() {
return ((bus_r(ADIF_CONFIG_REG) & ADIF_CONFIG_DBIT_PIPELINE_MSK) >>
ADIF_CONFIG_DBIT_PIPELINE_OFST);
}
int setPhase(enum CLKINDEX ind, int val, int degrees) {
if (ind < 0 || ind >= NUM_CLOCKS) {
LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));

28
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
View File

@ -550,7 +550,7 @@ void setupDetector() {
LOG(logERROR, ("%s\n\n", initErrorMessage));
initError = FAIL;
}
setPipeline(ADC_CLK, DEFAULT_PIPELINE);
setADCPipeline(DEFAULT_PIPELINE);
if (initError != FAIL) {
initError = loadPatternFile(DEFAULT_PATTERN_FILE, initErrorMessage);
}
@ -1562,35 +1562,23 @@ void configureSyncFrequency(enum CLKINDEX ind) {
setFrequency(SYNC_CLK, min);
}
// adc pipeline only
void setPipeline(enum CLKINDEX ind, int val) {
if (ind != ADC_CLK) {
LOG(logERROR, ("Unknown clock index %d to set pipeline\n", ind));
return;
}
void setADCPipeline(int val) {
if (val < 0) {
return;
}
LOG(logINFO, ("Setting adc clock (%d) Pipeline to %d\n", ADC_CLK, val));
uint32_t offset = ADC_OFFSET_ADC_PPLN_OFST;
uint32_t mask = ADC_OFFSET_ADC_PPLN_MSK;
LOG(logINFO, ("Setting adc pipeline to %d\n", val));
uint32_t addr = ADC_OFFSET_REG;
// reset value
bus_w(addr, bus_r(addr) & ~mask);
// set value
bus_w(addr, bus_r(addr) | ((val << offset) & mask));
LOG(logDEBUG1, (" adc clock (%d) Offset: 0x%8x\n", ADC_CLK, bus_r(addr)));
bus_w(addr, bus_r(addr) & ~ADC_OFFSET_ADC_PPLN_MSK);
bus_w(addr, bus_r(addr) | ((val << ADC_OFFSET_ADC_PPLN_OFST) &
ADC_OFFSET_ADC_PPLN_MSK));
}
int getPipeline(enum CLKINDEX ind) {
if (ind != ADC_CLK) {
LOG(logERROR, ("Unknown clock index %d to get pipeline\n", ind));
return -1;
}
int getADCPipeline() {
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_ADC_PPLN_MSK) >>
ADC_OFFSET_ADC_PPLN_OFST);
}
/* aquisition */
int startStateMachine() {

8
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
View File

@ -430,11 +430,13 @@ int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
void configureSyncFrequency(enum CLKINDEX ind);
void setPipeline(enum CLKINDEX ind, int val);
int getPipeline(enum CLKINDEX ind);
void setADCPipeline(int val);
int getADCPipeline();
#endif
#ifdef CHIPTESTBOARDD
void setDBITPipeline(int val);
int getDBITPipeline();
int setLEDEnable(int enable);
void setDigitalIODelay(uint64_t pinMask, int delay);
#endif
@ -519,6 +521,8 @@ int getClockDivider(enum CLKINDEX ind);
#elif GOTTHARD2D
int checkDetectorType();
int powerChip(int on);
void setDBITPipeline(int val);
int getDBITPipeline();
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);

8
slsDetectorServers/slsDetectorServer/include/slsDetectorServer_funcs.h
View File

@ -188,8 +188,6 @@ int get_clock_phase(int);
int get_max_clock_phase_shift(int);
int set_clock_divider(int);
int get_clock_divider(int);
int set_pipeline(int);
int get_pipeline(int);
int set_on_chip_dac(int);
int get_on_chip_dac(int);
int set_inject_channel(int);
@ -264,4 +262,8 @@ int set_comp_disable_time(int);
int get_flip_rows(int);
int set_flip_rows(int);
int get_filter_cell(int);
int set_filter_cell(int);
int set_filter_cell(int);
int set_adc_pipeline(int);
int get_adc_pipeline(int);
int set_dbit_pipeline(int);
int get_dbit_pipeline(int);

172
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
View File

@ -313,8 +313,6 @@ void function_table() {
flist[F_GET_MAX_CLOCK_PHASE_SHIFT] = &get_max_clock_phase_shift;
flist[F_SET_CLOCK_DIVIDER] = &set_clock_divider;
flist[F_GET_CLOCK_DIVIDER] = &get_clock_divider;
flist[F_SET_PIPELINE] = &set_pipeline;
flist[F_GET_PIPELINE] = &get_pipeline;
flist[F_SET_ON_CHIP_DAC] = &set_on_chip_dac;
flist[F_GET_ON_CHIP_DAC] = &get_on_chip_dac;
flist[F_SET_INJECT_CHANNEL] = &set_inject_channel;
@ -390,6 +388,10 @@ void function_table() {
flist[F_SET_FLIP_ROWS] = &set_flip_rows;
flist[F_GET_FILTER_CELL] = &get_filter_cell;
flist[F_SET_FILTER_CELL] = &set_filter_cell;
flist[F_SET_ADC_PIPELINE] = &set_adc_pipeline;
flist[F_GET_ADC_PIPELINE] = &get_adc_pipeline;
flist[F_SET_DBIT_PIPELINE] = &set_dbit_pipeline;
flist[F_GET_DBIT_PIPELINE] = &get_dbit_pipeline;
// check
if (NUM_DET_FUNCTIONS >= RECEIVER_ENUM_START) {
@ -6075,91 +6077,6 @@ int get_clock_divider(int file_des) {
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
}
int set_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int args[2] = {-1, -1};
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
LOG(logDEBUG1, ("Setting clock (%d) pipeline : %u\n", args[0], args[1]));
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
int ind = args[0];
int val = args[1];
enum CLKINDEX c = 0;
switch (ind) {
case ADC_CLOCK:
c = ADC_CLK;
break;
#ifdef CHIPTESTBOARDD
case DBIT_CLOCK:
c = DBIT_CLK;
break;
#endif
default:
modeNotImplemented("clock index (pipeline set)", ind);
break;
}
if (ret != FAIL) {
char *clock_names[] = {CLK_NAMES};
char modeName[50] = "";
sprintf(modeName, "%s clock (%d) piepline", clock_names[c], (int)c);
setPipeline(c, val);
int retval = getPipeline(c);
LOG(logDEBUG1, ("retval %s: %d\n", modeName, retval));
validate(&ret, mess, val, retval, modeName, DEC);
}
}
#endif
return Server_SendResult(file_des, INT32, NULL, 0);
}
int get_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int arg = -1;
int retval = -1;
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
LOG(logDEBUG1, ("Getting clock (%d) frequency\n", arg));
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
functionNotImplemented();
#else
// get only
enum CLKINDEX c = 0;
switch (arg) {
case ADC_CLOCK:
c = ADC_CLK;
break;
#ifdef CHIPTESTBOARDD
case DBIT_CLOCK:
c = DBIT_CLK;
break;
#endif
default:
modeNotImplemented("clock index (pipeline get)", arg);
break;
}
if (ret == OK) {
retval = getPipeline(c);
char *clock_names[] = {CLK_NAMES};
LOG(logDEBUG1, ("retval %s clock (%d) pipeline: %d\n", clock_names[c],
(int)c, retval));
}
#endif
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
}
int set_on_chip_dac(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
@ -8926,3 +8843,84 @@ int set_filter_cell(int file_des) {
#endif
return Server_SendResult(file_des, INT32, NULL, 0);
}
int set_adc_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int arg = -1;
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
LOG(logDEBUG1, ("Setting adc pipeline : %u\n", arg));
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
setADCPipeline(arg);
int retval = getADCPipeline();
LOG(logDEBUG1, ("retval adc pipeline: %d\n", retval));
validate(&ret, mess, arg, retval, "set adc pipeline", DEC);
}
#endif
return Server_SendResult(file_des, INT32, NULL, 0);
}
int get_adc_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int retval = -1;
LOG(logDEBUG1, ("Getting adc pipeline\n"));
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
functionNotImplemented();
#else
// get only
retval = getADCPipeline();
LOG(logDEBUG1, ("retval adc pipeline: %d\n", retval));
#endif
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
}
int set_dbit_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int arg = -1;
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
LOG(logDEBUG1, ("Setting dbit pipeline : %u\n", arg));
#if !defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
setDBITPipeline(arg);
int retval = getDBITPipeline();
LOG(logDEBUG1, ("retval dbit pipeline: %d\n", retval));
validate(&ret, mess, arg, retval, "set dbit pipeline", DEC);
}
#endif
return Server_SendResult(file_des, INT32, NULL, 0);
}
int get_dbit_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int retval = -1;
LOG(logDEBUG1, ("Getting dbit pipeline\n"));
#if !defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
retval = getDBITPipeline();
LOG(logDEBUG1, ("retval dbit pipeline: %d\n", retval));
#endif
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
}