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moench: default clocks and phase are same as ctb at startup

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This commit is contained in:
maliakal_d 2020-03-05 18:03:53 +01:00
parent 1d2a46cdbe
commit 959d62ed66
3 changed files with 20 additions and 7 deletions
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BIN
slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer
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19
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -445,11 +445,12 @@ void setupDetector() {
for (i = 0; i < NUM_CLOCKS; ++i) { for (i = 0; i < NUM_CLOCKS; ++i) {
clkPhase[i] = 0; clkPhase[i] = 0;
} }
clkFrequency[RUN_CLK] = DEFAULT_RUN_CLK; clkFrequency[RUN_CLK] = DEFAULT_RUN_CLK_AT_STARTUP;
clkFrequency[ADC_CLK] = DEFAULT_ADC_CLK; clkFrequency[ADC_CLK] = DEFAULT_ADC_CLK_AT_STARTUP;
clkFrequency[SYNC_CLK] = DEFAULT_SYNC_CLK; clkFrequency[SYNC_CLK] = DEFAULT_SYNC_CLK_AT_STARTUP;
clkFrequency[DBIT_CLK] = DEFAULT_DBIT_CLK; clkFrequency[DBIT_CLK] = DEFAULT_DBIT_CLK_AT_STARTUP;
// default adc phase in deg // default adc phase in deg
/*
{ {
int phase_shifts = 0; int phase_shifts = 0;
ConvertToDifferentRange(0, 359, 0, getMaxPhase(ADC_CLK) - 1, DEFAULT_ADC_PHASE_DEG, &phase_shifts); ConvertToDifferentRange(0, 359, 0, getMaxPhase(ADC_CLK) - 1, DEFAULT_ADC_PHASE_DEG, &phase_shifts);
@ -460,7 +461,7 @@ void setupDetector() {
FILE_LOG(logINFO, ("Default Sync clk: %d MHz\n", clkFrequency[SYNC_CLK])); FILE_LOG(logINFO, ("Default Sync clk: %d MHz\n", clkFrequency[SYNC_CLK]));
FILE_LOG(logINFO, ("Default Dbit clk: %d MHz\n", clkFrequency[DBIT_CLK])); FILE_LOG(logINFO, ("Default Dbit clk: %d MHz\n", clkFrequency[DBIT_CLK]));
FILE_LOG(logINFO, ("Default Adc Phase: %d (%d deg)\n", clkPhase[ADC_CLK], getPhase(ADC_CLK, 1))); FILE_LOG(logINFO, ("Default Adc Phase: %d (%d deg)\n", clkPhase[ADC_CLK], getPhase(ADC_CLK, 1)));
*/
for (i = 0; i < NDAC; ++i) for (i = 0; i < NDAC; ++i)
dacValues[i] = -1; dacValues[i] = -1;
} }
@ -525,6 +526,12 @@ void setupDetector() {
setPipeline(ADC_CLK, DEFAULT_PIPELINE); setPipeline(ADC_CLK, DEFAULT_PIPELINE);
loadDefaultPattern(DEFAULT_PATTERN_FILE); loadDefaultPattern(DEFAULT_PATTERN_FILE);
setSettings(DEFAULT_SETTINGS); setSettings(DEFAULT_SETTINGS);
setFrequency(RUN_CLK, DEFAULT_RUN_CLK);
setFrequency(ADC_CLK, DEFAULT_ADC_CLK);
setFrequency(DBIT_CLK, DEFAULT_DBIT_CLK);
setPhase(ADC_CLK, DEFAULT_ADC_PHASE_DEG, 1);
} }
int updateDatabytesandAllocateRAM() { int updateDatabytesandAllocateRAM() {
@ -1409,7 +1416,7 @@ int setFrequency(enum CLKINDEX ind, int val) {
return FAIL; return FAIL;
} }
char* clock_names[] = {CLK_NAMES}; char* clock_names[] = {CLK_NAMES};
FILE_LOG(logINFO, ("\tSetting %s clock (%d) frequency to %d MHz\n", clock_names[ind], ind, val)); FILE_LOG(logINFOBLUE, ("Setting %s clock (%d) frequency to %d MHz\n", clock_names[ind], ind, val));
// check adc clk too high // check adc clk too high
if (ind == ADC_CLK && val > MAXIMUM_ADC_CLK) { if (ind == ADC_CLK && val > MAXIMUM_ADC_CLK) {

8
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
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@ -73,11 +73,17 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define DEFAULT_VLIMIT (-100) #define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING) #define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a) #define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK_AT_STARTUP (200) // 40
#define DEFAULT_ADC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_SYNC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_DBIT_CLK_AT_STARTUP (200)
#define DEFAULT_RUN_CLK (40) #define DEFAULT_RUN_CLK (40)
#define DEFAULT_ADC_CLK (20) #define DEFAULT_ADC_CLK (20)
#define DEFAULT_SYNC_CLK (20)
#define DEFAULT_DBIT_CLK (40) #define DEFAULT_DBIT_CLK (40)
#define DEFAULT_ADC_PHASE_DEG (30) #define DEFAULT_ADC_PHASE_DEG (30)
#define DEFAULT_PIPELINE (14) #define DEFAULT_PIPELINE (14)
#define DEFAULT_SETTINGS (G4_HIGHGAIN) #define DEFAULT_SETTINGS (G4_HIGHGAIN)