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changes to gotthard server to include write adc, and also changes to fix the dma=dma+1

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This commit is contained in:
Dhanya Maliakal
2017-07-11 10:54:21 +02:00
parent a583f3d6e2
commit 931a5840e8
14 changed files with 397 additions and 291 deletions
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1
slsDetectorSoftware/gotthardDetectorServer/AD9257.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/AD9257.h

2
slsDetectorSoftware/gotthardDetectorServer/Makefile
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@ -16,7 +16,7 @@ INSTMODE= 0777
BINS = testlib_sharedlibc
SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c mcb_funcs.c trimming_funcs.c sharedmemory.c
SRCS = server.c firmware_funcs.c server_funcs.c communication_funcs.c mcb_funcs.c trimming_funcs.c sharedmemory.c
OBJS = $(SRCS:%.c=%.o)

1
slsDetectorSoftware/gotthardDetectorServer/commonServerFunctions.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/commonServerFunctions.h

54
slsDetectorSoftware/gotthardDetectorServer/firmware_funcs.c
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@ -4,6 +4,8 @@
#include "mcb_funcs.h"
#include "registers_g.h"
#include "AD9257.h" // include "commonServerFunctions.h"
#ifdef SHAREDMEMORY
#include "sharedmemory.h"
#endif
@ -1814,7 +1816,9 @@ int allocateRAM() {
}
int prepareADC(){
int configureADC(){
printf("Preparing ADC\n");
u_int32_t valw,codata,csmask;
int i,j,cdx,ddx;
@ -1834,26 +1838,26 @@ int prepareADC(){
// start point
valw=0xff;
bus_w(ADC_WRITE_REG,(valw));
bus_w(ADC_SPI_REG,(valw));
//chip sel bar down
valw=((0xffffffff&(~csmask)));
bus_w(ADC_WRITE_REG,valw);
bus_w(ADC_SPI_REG,valw);
for (i=0;i<24;i++) {
//cldwn
valw=valw&(~(0x1<<cdx));
bus_w(ADC_WRITE_REG,valw);
bus_w(ADC_SPI_REG,valw);
usleep(0);
//write data (i)
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx);
bus_w(ADC_WRITE_REG,valw);
bus_w(ADC_SPI_REG,valw);
usleep(0);
//clkup
valw=valw+(0x1<<cdx);
bus_w(ADC_WRITE_REG,valw);
bus_w(ADC_SPI_REG,valw);
usleep(0);
}
@ -1861,7 +1865,7 @@ int prepareADC(){
valw=valw&(~(0x1<<cdx));
usleep(0);
valw=0xff;
bus_w(ADC_WRITE_REG,(valw));
bus_w(ADC_SPI_REG,(valw));
//usleep in between
usleep(50000);
@ -1872,19 +1876,19 @@ int prepareADC(){
/*
codata=0;
codata=(0x14<<8)+(0x0); //command and value;
valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // start point
valw=((0xffffffff&(~csmask)));bus_w(ADC_WRITE_REG,valw); //chip sel bar down
valw=0xff; bus_w(ADC_SPI_REG,(valw)); // start point
valw=((0xffffffff&(~csmask)));bus_w(ADC_SPI_REG,valw); //chip sel bar down
for (i=0;i<24;i++) {
valw=valw&(~(0x1<<cdx));bus_w(ADC_WRITE_REG,valw);usleep(0); //cldwn
valw=valw&(~(0x1<<cdx));bus_w(ADC_SPI_REG,valw);usleep(0); //cldwn
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); bus_w(ADC_WRITE_REG,valw); usleep(0); //write data (i)
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); bus_w(ADC_SPI_REG,valw); usleep(0); //write data (i)
valw=valw+(0x1<<cdx);bus_w(ADC_WRITE_REG,valw); usleep(0); //clkup
valw=valw+(0x1<<cdx);bus_w(ADC_SPI_REG,valw); usleep(0); //clkup
}
valw=valw&(~(0x1<<cdx));usleep(0);
valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // stop point =start point
valw=0xff; bus_w(ADC_SPI_REG,(valw)); // stop point =start point
@ -1892,36 +1896,36 @@ int prepareADC(){
codata=0;
codata=(0x08<<8)+(0x3); //command and value;Power modes(global) reset
valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // start point
valw=((0xffffffff&(~csmask)));bus_w(ADC_WRITE_REG,valw); //chip sel bar down
valw=0xff; bus_w(ADC_SPI_REG,(valw)); // start point
valw=((0xffffffff&(~csmask)));bus_w(ADC_SPI_REG,valw); //chip sel bar down
for (i=0;i<24;i++) {
valw=valw&(~(0x1<<cdx));bus_w(ADC_WRITE_REG,valw);usleep(0); //cldwn
valw=valw&(~(0x1<<cdx));bus_w(ADC_SPI_REG,valw);usleep(0); //cldwn
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); bus_w(ADC_WRITE_REG,valw); usleep(0); //write data (i)
valw=valw+(0x1<<cdx);bus_w(ADC_WRITE_REG,valw); usleep(0); //clkup
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); bus_w(ADC_SPI_REG,valw); usleep(0); //write data (i)
valw=valw+(0x1<<cdx);bus_w(ADC_SPI_REG,valw); usleep(0); //clkup
}
valw=valw&(~(0x1<<cdx));usleep(0);
valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // stop point =start point
valw=0xff; bus_w(ADC_SPI_REG,(valw)); // stop point =start point
usleep(50000);
codata=0;
codata=(0x08<<8)+(0x0); //command and value;Power modes(global) reset
valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // start point
valw=((0xffffffff&(~csmask)));bus_w(ADC_WRITE_REG,valw); //chip sel bar down
valw=0xff; bus_w(ADC_SPI_REG,(valw)); // start point
valw=((0xffffffff&(~csmask)));bus_w(ADC_SPI_REG,valw); //chip sel bar down
for (i=0;i<24;i++) {
valw=valw&(~(0x1<<cdx));bus_w(ADC_WRITE_REG,valw);usleep(0); //cldwn
valw=valw&(~(0x1<<cdx));bus_w(ADC_SPI_REG,valw);usleep(0); //cldwn
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); bus_w(ADC_WRITE_REG,valw); usleep(0); //write data (i)
valw=valw+(0x1<<cdx);bus_w(ADC_WRITE_REG,valw); usleep(0); //clkup
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); bus_w(ADC_SPI_REG,valw); usleep(0); //write data (i)
valw=valw+(0x1<<cdx);bus_w(ADC_SPI_REG,valw); usleep(0); //clkup
}
valw=valw&(~(0x1<<cdx));usleep(0);
valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // stop point =start point
valw=0xff; bus_w(ADC_SPI_REG,(valw)); // stop point =start point
*/
}

1
slsDetectorSoftware/gotthardDetectorServer/firmware_funcs.h
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@ -139,6 +139,7 @@ int allocateRAM();
int clearRAM();
int setMaster(int f);
int setSynchronization(int s);

BIN
slsDetectorSoftware/gotthardDetectorServer/gotthardDetectorServerv3.0.0.0
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slsDetectorSoftware/gotthardDetectorServer/gotthardDetectorServerv3.0.0.1 Executable file
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11
slsDetectorSoftware/gotthardDetectorServer/registers_g.h
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@ -33,7 +33,16 @@
//#define TIME_FROM_START_REG 0x16<<11
#define MCB_CNTRL_REG_OFF 0x17<<11// control the dacs
//ADC
#define ADC_WRITE_REG 0x18<<11
#define ADC_SPI_REG 0x18<<11
#define ADC_SERIAL_CLK_OUT_OFST (0)
#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
#define ADC_SERIAL_DATA_OUT_OFST (1)
#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
#define ADC_SERIAL_CS_OUT_OFST (2)
#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
#define ADC_SYNC_REG 0x19<<11
//#define MUTIME_REG 0x1a<<11
//temperature

54
slsDetectorSoftware/gotthardDetectorServer/server_funcs.c
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@ -84,7 +84,7 @@ int init_detector( int b) {
//gotthard specific
setPhaseShiftOnce();
prepareADC();
configureADC();
setADC(-1); //already does setdaqreg and clean fifo
setSettings(GET_SETTINGS,-1);
@ -192,6 +192,7 @@ int function_table() {
flist[F_PREPARE_ACQUISITION]=&start_receiver;
flist[F_CLEANUP_ACQUISITION]=&stop_receiver;
flist[F_CALIBRATE_PEDESTAL]=&calibrate_pedestal;
flist[F_WRITE_ADC_REG]=&write_adc_register;
return OK;
}
@ -3055,3 +3056,54 @@ int calibrate_pedestal(int file_des){
}
int write_adc_register(int file_des) {
int ret=OK;
int n=0;
int retval=-1;
sprintf(mess,"write to adc register failed\n");
// receive arguments
int arg[2]={-1,-1};
n = receiveData(file_des,arg,sizeof(arg),INT32);
if (n < 0) {
sprintf(mess,"Error reading from socket\n");
ret=FAIL;
}
int addr=arg[0];
int val=arg[1];
// execute action
if (ret == OK) {
if (differentClients && lockStatus) {
ret = FAIL;
sprintf(mess,"Detector locked by %s\n",lastClientIP);
cprintf(RED, "Warning: %s", mess);
}
else {
#ifdef VERBOSE
printf("writing to register 0x%x data 0x%x\n", addr, val);
#endif
setAdc(addr,val);
#ifdef VERBOSE
printf("Data set to 0x%x\n", retval);
#endif
if (ret==OK && differentClients)
ret=FORCE_UPDATE;
}
}
// send ok / fail
n = sendDataOnly(file_des,&ret,sizeof(ret));
// send return argument
if (ret==FAIL) {
n = sendDataOnly(file_des,mess,sizeof(mess));
} else
n = sendDataOnly(file_des,&retval,sizeof(retval));
// return ok / fail
return ret;
}

4
slsDetectorSoftware/gotthardDetectorServer/server_funcs.h
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@ -69,7 +69,7 @@ int set_dynamic_range(int);
int set_roi(int);
int get_roi(int);
int set_speed(int);
void prepareADC(void);
void configureADC();
int set_readout_flags(int);
int execute_trimming(int);
int lock_server(int);
@ -94,4 +94,6 @@ int calibrate_pedestal(int);
int set_roi(int);
int write_adc_register(int);
#endif